/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 * =======================================================================
 *  This file contains the code that sets up the NET+ARM chip selects.
 *  THE CODE IN THIS FILE MUST BE CUSTOMIZED TO SUPPORT YOUR APPLICATION
 *  HARDWARE.  The default implementation supports the NET+OS development
 *  boards.  These boards have flash attached to CS0, RAM attached to CS1,
 *  possibly more RAM attached to CS2, and maybe an EEPROM attached to
 *  CS3.
 *
 *
 *
 * Edit Date/Ver   Edit Description
 * ==============  =======================================================
 *
 * 05/20/03 JZW     Added include of sysClock.h to pick up functional prototype
 *                  of NaGetXtalFreq
 */


#include <Npttypes.h>
#include <bsp_arm7refs.h>
#include <bsp_sys.h>
#include <reg_def.h>
#include <ncc_init.h>
#include <gen_def.h>
#include <errhndlr.h>
#include <cs.h>
#include <sysClock.h>
#include <appconf_api.h> /* for NAgetAppUseNvram */
#include "ncc_init.h"

unsigned long heap_adjustment = 0;


/*ad*
 * The NET+OS BSP contains a set of functions that usually
 * need to be customized to support specific hardware.  The 
 * default implementations support the NET+OS development
 * boards.  You must modify them to support your application's
 * hardware.
 *
 * The customization hooks are located in the following files.
 * <list type="unordered">
 *      <item>cs.c contains the code that sets up the NET+ARM chip selects to
 *            support the memory parts on your board.  The default implementation
 *            sets up CS0 to support 2 Megs of flash, and CS1 and CS2 to support
 *            RAM. </item>
 *      <item>gpio.c contains the code that sets up the GPIO ports.  These need
 *            to be configured to support serial port functions, DMA handshake
 *            signals, LEDs, interrupt requests, or other I/O signals.</item>
 *      <item>dialog.c contains the code that displays the development board's
 *            configuration dialog.  Usually you should disable the dialog in most
 *            shipping applications.</item>
 *      <item>boardParams.c and aceParams.c contain functions that read and write
 *            to NVRAM.  You must update these functions to support your application's
 *            usage of NVRAM.</item>
 * </list>
 *
 *
 * @category BSP_CustomizationHooks
 * @since 6.0
 * @overview BSP Customization Hooks
 * @external
*ad*/


/*ad*
 * This function must return an appropriate value for the System
 * Control Register in the GEN module.  This version of the function
 * is written to support NET+OS development boards.  SCR should be
 * set up as follows on these boards.
 *
 *	<list type = "unordered">
 *     <item> lendian     = (leave as read from ADDR27 at power up) </item>
 *     <item> bspeed      = full speed </item>
 *     <item> swe         = watchdog disabled </item>
 *     <item> swri        = watchdog disabled </item>
 *     <item> swt         = watchdog disabled  </item>
 *     <item> bme         = enable bus monitor </item>
 *     <item> bmt         = bus monitor timeout 32 BCLKs </item>
 *     <item> user        = allow users to access ASIC registers </item>
 *     <item> buser       = don't allow external bus master to access ASIC registers </item>
 *     <item> iarb        = set internal IARB </item>
 *     <item> dmatst      = (don't change, will be set when this function is called) </item>
 *     <item> tea_last    = use TEA pin for error indication only </item>
 *     <item> misalign    = disable misalign transfer bus abort generation </item>
 *     <item> cache       = leave cache disabled for now </item>
 *     <item> cinit       = don't set cache init bit </item>
 *     <item> dmarst      = don't reset the DMA module </item>
 *     <item> bsync       = 1 stage Synchronizer </item>
 *  </list>
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @return  value to write into System Control Register
*ad*/
WORD32 customizeGetScr(void) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    WORD32 regValue = *NARM_GSCR_ADDR & (GEN_SCR_LENDIAN | GEN_SCR_DMATST);

    regValue |= GEN_SCR_BSPEED_FULL | GEN_SCR_BME | GEN_SCR_BMT_128_BCLKS | GEN_SCR_USER | GEN_SCR_IARB_INTERNAL;
	 	 
    return regValue;
}











/*ad*
 * This function creates an appropriate mask that can be written into 
 * the chip select option register.  If the mask is used, it will setup
 * the chip select to support the amount of RAM indicated by the
 * parameter size.
 *
 *
 * This version of the function is for the NET+OS development boards.
 * A special mask is used on these boards that causes the memory
 * connected to a chip select to appear in 4 different places in the
 * address space.  This is used to control caching.
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param size        number of bytes of RAM connected to the CS
 *
 * @return value for mask field of CSOR register
*ad*/
WORD32 customizeCreateMask(WORD32 size)
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    WORD32 mask;

    mask = ~size + 1;               /* compute raw mask*/
    mask &= BSP_CACHE_MASK;         /* adjust mask to support NET+OS caching*/

    return mask;
}










/*ad*
 * This routine returns the total number of bytes of memory
 * the chip select is configured to support.  It does this
 * by examining the address mask in the CS option register.
 *
 *
 * This routine was written to support the NET+OS development
 * board and NET+OS.  NET+OS normally sets up the address 
 * masks so that a part's memory appears in the address space
 * four times.  This is done to support caching.  This function
 * takes this into account when it calculates the amount of
 * memory connected to the CS.
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.  You will need to
 * modify this function if you are using a nonstandard cache setup.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param csarAddress     address of the address register for this CS
 * @param csorAddress     address of the option register for this CS
 *
 * @return number of bytes of memory the CS is configured for
*ad*/
WORD32 customizeGetCSSize(WORD32 * csarAddress, WORD32 * csorAddress)
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    WORD32 mask, size = 0;

    if (narm_read_reg(NARM_CSAR_REG, csarAddress, v) == TRUE)
    {                                       /* if chip select valid bit is set*/
        mask = narm_read_reg(NARM_CSOR_REG, csorAddress, mask) << CS_BASE_MASK_SHIFT;
                                            /* then read the mask value*/
        mask |= ~BSP_CACHE_MASK;            /* get rid of the cache bits in the mask*/
        size = (~mask) + 1;                 /* determine the size of the part*/
    }

    return size;
}





/*ad*
 * This routine returns the total number of bytes of RAM on the board.
 * This function is called if the BSP initialization code detects that
 * the chip selects have already been configured.  Instead of
 * reconfiguring them and possibly destroying variables in RAM, the init
 * code will call this function to determine how much RAM is on the
 * board.
 *
 *
 * This version is written to support NET+OS development boards.  These
 * boards have RAM on CS1, and possibly CS2.  We determine the amount
 * of RAM by examining the mask value in the option registers for these
 * chip selects.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @return amount of available RAM in bytes
*ad*/
WORD32 customizeGetRamSize(void)
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    WORD32 size;

    /*
     * RAM should be attached to CS1, and possibly CS2.
     */
    size = customizeGetCSSize((WORD32 *)NARM_CSAR1_ADDR, (WORD32 *)NARM_CSOR1_ADDR);
    size += customizeGetCSSize((WORD32 *)NARM_CSAR2_ADDR, (WORD32 *)NARM_CSOR2_ADDR);

    return size;
}










/*ad*
 * This function sets up the memory management control register.
 * The MMCR controls the DRAM refresh timing and special functions
 * for A27, A26, and A25.  Default functionality for the A27 and A26
 * pins is set by H/W through pull down resisters on A24 and A23.
 * Usually, software should leave the power up settings for these
 * pins alone.
 *
 *
 * This version of this function sets up the MMCR for the NET+OS
 * development board.  The DRAM refresh is setup for a 15 us period.
 * A25 is programmed to act as address pin 25.  AMUX and AMUX2 are
 * disabled.  A27 and A26 are left in their power up settings.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.  If you followed the 
 * NET+OS design guidelines in your H/W design, then you should be 
 * able to use this function as is for your H/W.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
*ad*/
void customizeSetupMMCR(void)
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
/*  
 * Dynamic RAM Refresh Counter Adjustment
 * Set to 66666 Hz (15 usec rate) which works on every DRAM part we know of
 * Rate = ((refcnt + 1) * 4 ) / Fxtal
 *
 * Use refcnt = Fxtal/(66666 * 4) -- ignore the "+ 1" to compensate for round off.
 */
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, rfcnt, NAgetSysOscFreq
() / 266666);
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, rcyc, NARM_MMCR_RCYC_5_BCLK);
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, refen, TRUE);

/*
 * Setup A25 to act as A25.
 */
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, a25, FALSE);

/*
 * Disable AMUX and AMUX2.
 */
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, amux, FALSE);
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, amux2, FALSE);

/*
 * Setup the A26 and A27 signals
 */
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, a26, FALSE);
    narm_write_reg(NARM_MMCR_REG, NARM_MMCR_ADDR, a27, FALSE);

}







/*ad*
 * This function must setup CS0.  CS0 will have its power up
 * value when this function is called.  This value is determined
 * by whether pins A24 and A23 are pulled up or pulled down.  This
 * is explained in the chapter on Bootstrap Initialization in
 * the hardware reference guide.
 *
 *
 * The NET+ARM configures CS0 to support memory and starts executing
 * code from it.  This means CS0 will almost always be connected to
 * flash or ROM.  It is possible to connect it to RAM if the RAM is
 * already initialized before the NET+ARM powers up.
 *
 *
 * This version of the code initializes CS0 to support the NET+OS
 * development board.  These boards can have either 2 Meg of 16-bit
 * wide flash, or 4 Megs of 32-bit wide flash.  The CS is configured
 * for the part according to values in the file settings.c.  If your
 * system configuration is similar to the development board, then
 * you may be able to make this function work for your board by
 * just adjusting the values in settings.c.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param ramSize       pointer to in loaded with amount of RAM found so
 *                      far.  
*ad*/
void customizeSetupCS0(WORD32 * ramSize) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    WORD32 csor = 0, csar = 0, flash_size;
    int idx, port_size;

    NA_UNUSED_PARAM(ramSize);   /* To remove GNU Compiler warning. */

    /* if we are running from flash, we should use the flashSize in the linker file */
    if (nccRomImageBuild() == 1)
    {
        flash_size = (WORD32)&_NABspFlashSize; /* flashSize specified from ld */
    }
    else
    {
        flash_size = (WORD32)NABspFlashSize; /* software specifies the flash size */
    }
	/*  develop the idx into the NetarmInitData aray  */
    idx  = narm_read_reg(NARM_GSSR_REG, NARM_GSSR_ADDR, rev);

    /*
     * We have to be a little careful in this function since we will be 
     * executing code from ROM while we are setting up this CS which
     * controls ROM.  For safety sake, we will build up words in local
     * memory and then write to the chip select at the end of this function.
     * 
     * Set base address of ROM.
     */
	narm_write_reg (NARM_CSAR_REG, &csar, base, BSP_ROM_BASE >> CS_BASE_MASK_SHIFT);

    /*
     * Set the mask for the chip select.  The mask determines the size of the
     * part.  Note that we set up the mask so that the part appears
     * in four places in the NET+ARM's address space.  This is done for
     * caching.
     */
	if (nccRomImageBuild() == 1 && narm_read_reg (NARM_CSOR_REG, NARM_CSOR0_ADDR, ps) ==0)
    {
		/*  32-bit, 2M flash    */
        port_size = 2;
    }
    else
    {
        port_size = 1;
    }

    narm_write_reg (NARM_CSOR_REG, &csor, mask, customizeCreateMask(port_size * flash_size) >> CS_BASE_MASK_SHIFT);

    /*  save the option register mask -- flash size */
    csor |= (*NARM_CSOR0_ADDR & 0xfff) & ~(NAOptRegWaitAndBurstMask + NAOptRegRsyncMask);
 

    /*  Set the number of wait states, bsize and bcyc for Flash */
    narm_write_reg (NARM_CSOR_REG, &csor, wait, NANetarmInitData[idx].cs0WaitStates);
    narm_write_reg (NARM_CSOR_REG, &csor, bcyc, NANetarmInitData[idx].cs0BusCycles);
    narm_write_reg (NARM_CSOR_REG, &csor, bsize, NANetarmInitData[idx].cs0bsize);

    /*  At slower speeds you can use the rsync bit to speed things up  */
    narm_write_reg (NARM_CSOR_REG, &csor, rsync, NANetarmInitData[idx].cs0UseRsync);


    /*  at 33 Mhz -- we can burst the flash */
    narm_write_reg (NARM_CSAR_REG, &csar, burst, NANetarmInitData[idx].cs0AddRegBurst);

    csar |= narm_read_reg (NARM_CSAR_REG, NARM_CSAR0_ADDR, v);

    /*
     * Program the chip select.  CS0 is special.  Normally you write the option register before
     * writing the base address register.  But on CS0 you write CSBAR0 before CSOR0.  The 
     * chip select H/W in the chip lets you do this so that you can update the register 
     * while executing code in it.
     */
    *NARM_CSAR0_ADDR = csar;
    *NARM_CSOR0_ADDR = csor;
	
	narm_write_reg (NARM_CSORB_REG, NARM_CSORB0_ADDR, wait, 0);
	narm_write_reg (NARM_CSORB_REG, NARM_CSORB0_ADDR, bcyc, 1);
}





/*ad*
 * This function must setup CS1.  CS1 will be disabled at power up.
 *
 *
 * This version of the code initializes CS1 to support the NET+OS
 * development board.  These boards have RAM connected to CS1.  This
 * function determines the type of RAM and how much is present and 
 * then configures the chip select accordingly.  RAM attached to
 * CS1 is mapped to start at address 0. 
 *
 *
 * NET+OS supports a maximum of 32 Megabytes of RAM.  If more than 
 * that is used, then the cache driver will have to be adjusted.
 *
 *
 * The SDRAM controller supports a maximum of 128 Megs.  If more
 * SDRAM than that will be attached to a single chip select, then
 * an external controller must be used.
 *
 *
 * This function uses values in settings.c to configure the chip
 * select.  If your board also attaches RAM to CS1 (as recommended
 * in the design guidelines), then you should be able to use this
 * function as is and just change the values in settings.c for
 * your particular board.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param ramSize   pointer to in loaded with amount of RAM found so
 *                  far.  This function will update this value with the
 *                  amount of RAM found on CS1.
*ad*/
void customizeSetupCS1(WORD32 * ramSize) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    /*
     * Determine the type of RAM attached to the chip select.  The values in
     * NANetarmInitData inside of settings.c are used to program the chip
     * select to properly support the RAM.
     */

    if (nccDetermineRamType(NARM_CSAR1_ADDR, NARM_CSOR1_ADDR, *ramSize, CS_32_MEGS) == NCC_NO_RAM)
    {
        /*
         * All development boards must have RAM attached to CS1.  Call the error
         * handler and die if there isn't any.
         */
        customizeErrorHandler(ERROR_RAM_FAILURE, ERROR_SUBCODE_NO_RAM); 
    }
 
    /*
     * At this point the chip select has been progammed to support 64 Megs of RAM.
     * The settings for wait states and stuff have been set according to the
     * values in NANetarmInitData.  Now figure out how much RAM is actually attached
     * to the chip select and reconfigure it accordingly.
     *
     * NET+OS supports a maximum of 32 Megabytes of RAM.  If more than that is used, then
     * the cache driver will have to be adjusted.
     *
     * The SDRAM controller supports a maximum of 128 Megs.  If more SDRAM than that
     * will be attached to a single chip select, then an external controller must be
     * used.
     */
    *ramSize = nccDetermineRamSize(NARM_CSAR1_ADDR, NARM_CSOR1_ADDR, *ramSize, CS_32_MEGS); 
    
	narm_write_reg (NARM_CSORB_REG, NARM_CSORB1_ADDR, wait, 0);
	narm_write_reg (NARM_CSORB_REG, NARM_CSORB1_ADDR, bcyc, 0);
}







/*ad*
 * This function must setup CS2.  CS2 will be disabled at power up.
 *
 *
 * This version of the code initializes CS2 to support the NET+OS
 * development board.  On these boards, CS1 is used to support RAM.
 * CS2 may be used to support additional RAM.  If so, then the 
 * NET+ARM memory controller requires that it be the same type
 * of RAM attached to CS1 (see the description of the DMODE field
 * of the CSBAR register in the H/W reference manual).
 *
 *
 * This function sets up CS2 with the same settings that CS1 has
 * and tests for the presence of RAM.  If some is found, then
 * the RAM is sized and the CS settings updated.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param ramSize   pointer to in loaded with amount of RAM found on
 *                  CS1.  If RAM is found on CS2, then this function 
 *                  will setup CS2 so that it appears immediately after
 *                  CS1, and *ramSize will be updated to reflect the
 *                  total amount of RAM available.
*ad*/
void customizeSetupCS2(WORD32 * ramSize) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */
    /*
     * Copy the chip select settings from CS1 and see if there is RAM attached to
     * CS2.
     */
    if (nccCopyCSSetup(NARM_CSAR2_ADDR, NARM_CSOR2_ADDR, NARM_CSAR1_ADDR, NARM_CSOR1_ADDR, *ramSize) == NCC_RAM_DETECTED)
    {
        /*
         * At this point the chip select has been progammed to support RAM.
         * The settings for wait states and stuff have been set according to the
         * values in NANetarmInitData.  Now figure out how much RAM is actually attached
         * to the chip select and reconfigure it accordingly.
         *
         * NET+OS supports a maximum of 64 Megabytes of RAM.  If more than that is used, then
         * the cache driver will have to be adjusted.
         */
        *ramSize = nccDetermineRamSize(NARM_CSAR2_ADDR, NARM_CSOR2_ADDR, *ramSize, CS_32_MEGS);
    }

	narm_write_reg (NARM_CSORB_REG, NARM_CSORB2_ADDR, wait, 0);
	narm_write_reg (NARM_CSORB_REG, NARM_CSORB2_ADDR, bcyc, 0);
}






/*ad*
 * This function must setup CS3.  CS3 will be disabled at power up.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param ramSize   pointer to in loaded with amount of RAM found so
 *                  far.
*ad*/

void customizeSetupCS3(WORD32 * ramSize) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */

    NA_UNUSED_PARAM(ramSize);   /* To remove GNU Compiler warning. */

    /*
     * NS7520 development board has nothing attached to CS3.
     */
    *NARM_CSAR3_ADDR = 0;
    *NARM_CSOR3_ADDR = 0;
    *NARM_CSORB3_ADDR = 0;
}





/*ad*
 * This function must setup CS4.  CS4 will be disabled at power up.
 *
 *
 * This version of the code initializes CS4 to support the NET+OS
 * development board.  CS4 is not used on these boards and so is
 * disabled by this function.
 *
 *
 * @note THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  The implementation
 * below is for NET+OS development boards only.
 *
 * This function will be called by ncc_init() before RAM has been
 * configured.  The stack will be located on internal RAM in the
 * NET+ARM.  You can only use stack variables.  Do not use global
 * or static variables.
 *
 * @external
 * @category BSP_CustomizationHooks
 * @since 5.1
 *
 * @param ramSize   pointer to in loaded with amount of RAM found so
 *                  far.
*ad*/

void customizeSetupCS4(WORD32 * ramSize) 
{
/*
 * THIS CODE MUST BE CUSTOMIZED FOR YOUR BOARD.  This implementation
 * is for NET+OS development boards only.
 */

    NA_UNUSED_PARAM(ramSize);   /* To remove GNU Compiler warning. */


    /*
     * The chip select is not used on the development board.  Make sure it is
     * disabled.
     */
     *NARM_CSAR4_ADDR = 0;
     *NARM_CSOR4_ADDR = 0;
     *NARM_CSORB4_ADDR = 0;
}

/*ad*
 *  This function is called to update any CS1 after RAM and FLASH has initialized.
 *  This is usually called to update the actual size of the FLASH after flash driver
 *  is initialized.
 *
*ad*/
void customizeUpdateCS(void) 
{
    WORD32 flashSize;

    /* no need to update cs for flash if running from rom */    
    customizeSetupCS0(&flashSize) ;
    return;
}








