/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 * Description.
 * =======================================================================
 * This file contains the public API for the SYSCLK and XTAL1 clock.  These
 * values should be updated and defined for each peculiar board support 
 * package.  Be aware that the values for the Crystal or XTAL input have 
 * huge ramifications on the system timing, in particular, serial data 
 * transfer rates.
 *                                                                        
 *                                                                        
 * Edit Date/Ver   Edit Description
 * ==============  ===================================================
 * PMJ  04/30/01   Set PLLTST_SELECT to the NA_SELECT_THE_CRYSTAL_INPUT
 *                 (the oscillator input).
 * PMJ  06/06/01   Redefined PLLTST_SELECT and PLL_CONTROL_REGISTER_N_VALUE to
 *                 use values based within the chip select system settings.  This
 *                 allows auto-sensing of the chip type, for those systems using
 *                 multiple configurations of hardware. (see Settings.h)
 *
 */
#ifndef __SYSCLOCK_H
#define __SYSCLOCK_H

#ifdef __cplusplus
extern "C"
{
#endif

#include <bsp_api.h>
#include <sysClockApi.h>

/*ad*
 * SYSCLK clock sources
 *
 * @external
 * @category BSP_Configuration
 * @since 6.0
 * @name SYSCLK_SRC     "System Clock Sources"
 *
 * @param NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT              Use the XTAL input as the SYSCLK signal.
 * @param NA_SELECT_THE_CRYSTAL_INPUT Use the internal PLL to generate SYSCLK.
*ad*/
    
#define NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT              0
#define NA_SELECT_THE_CRYSTAL_INPUT 1

/*ad*
 *      Determines the clock source to be used    This directive is 
 *      the address input to the SYSCLK signal multiplexer.  The SYSCLK 
 *      has two possible sources: one from the TTL clock input applied 
 *      to the XTAL1 pin and the other from the crystal oscillator and 
 *      phase lock loop (PLL) circuit.
 *
 *
 *      When PLLTST_SELECT = NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT
 *
 *          SYSCLK uses the XTAL1 its source.
 *
 *
 *      When PLLTST_SELECT = NA_SELECT_THE_CRYSTAL_INPUT
 *
 *          SYSCLK uses the Crystal Ocsillator and PLL as its source.
 *
 * @external
 * @category SYSCLK
 * @since 6.0
 *
 * @see @link SYSCLK_SRC
*ad*/
#define PLLTST_SELECT                       NAusesTheInternalOscillator()



/*ad*
 *      Indicates the frequency of the TTL clock input 
 *      applied to the XTAL1 pin   
 *
 *      This clock signal is used to 
 *      generate the internal SYSCLK signal if and only if the 
 *      PLLTST_SELECT is set to NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT.  Otherwise, 
 *      the value is a don't care.
 *
 * @external
 * @category SYSCLK
 * @since 6.0
 * @name XTAL1_FREQUENCY        "Clock Frequencies"
 *
 * @param XTAL1_FREQUENCY                     33177600
 * @param XTAL1_FREQUENCY_20UM                55000000
*ad*/
    
#define XTAL1_FREQUENCY                     33177600
#define XTAL1_FREQUENCY_20UM                55000000  /*for 20UM  LZ*/



/*ad*
 *      Indicates the frequency of the crystal 
 *      oscillator   
 *
 *      This signal generates an input to the 
 *      phase lock loop (PLL), and along with the register value 
 *      (PLL_CONTROL_REGISTER_N_VALUE) PLLCNT in the PLL control 
 *      register, CRYSTAL_OSCILLATOR_FREQUENCY determines the frequency 
 *      of the internal SYSCLK signal if and only if the PLLTST_SELECT is set to 
 *      NA_SELECT_THE_CRYSTAL_INPUT.  Otherwise, the value is 
 *      a don't care.
 *
 * @external
 * @category SYSCLK
 * @since 6.0
 *
 * @see @link SYSCLK_SRC
*ad*/
#ifdef BSP_921K_CONNECTME_SUPPORT
#define CRYSTAL_OSCILLATOR_FREQUENCY        19660800
#else
#define CRYSTAL_OSCILLATOR_FREQUENCY        18432000
#endif

/* 
 *  The following directives are used in the NetarmInitData settings table.  
 *  If the XTAL1 input or Crytsal Oscillator Frequency change, then these 
 *  should be adjusted accordingly.  These values represent the PLL count 
 *  required to generate 33 and 44 Mhz.
 *
 */
#define _33MHZ                              6
#define _44MHZ                              9
#define _55MHZ                              7


#ifdef __cplusplus
}
#endif
#endif


