/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 *  Description.
 *
 *  This file contains the public API code that sets up the GPIO ports.  THE
 *  DEFINITIONS IN THIS FILE AND THE SOURCE CODE FOR THIS INTERFACE SHOULD BE 
 *  CUSTOMIZED FOR YOUR PARTICULAR HARDWARE.  The version of the file that is 
 *  shipped with the NET+OS BSP is written to support NET+OS development boards.  
 *  Your hardware will be different and the code in this file must be 
 *  customized to support it.
 *
 *
 * Edit Date/Ver   Edit Description
 * ==============  =======================================================
 *
 *
 */


#ifndef __GPIO_H_
#define __GPIO_H_

#include <gpiomux_def.h>
#if !defined(INIT_ARM)
    #include "bsp.h"
#endif

#ifdef __cplusplus
extern "C"
{
#endif

/*ad*
 * Set this constant to indicate the data bus width on your board.  The data bus
 * width is selected in hardware through strapping pins.  You must set this 
 * constant to match the data bus width selected by the hardware strapping
 * pins.
 *
 * Set BSP_GPIO_MUX_DATA_BUS_WIDTH to BSP_GPIO_MUX_DATA_BUS_WIDTH_16 if a 16-bit
 * data bus width has been selected, or to BSP_GPIO_MUX_DATA_BUS_WIDTH_32 if a
 * 32-bit bus width has been selected.
 *
 * @since 7.3
 * @external
 * @category Mux_and_GPIO
 * @overview Signal Multiplexing and GPIO
*ad*/
#define BSP_GPIO_MUX_DATA_BUS_WIDTH BSP_GPIO_MUX_DATA_BUS_WIDTH_16

#if (BSP_GPIO_MUX_DATA_BUS_WIDTH != BSP_GPIO_MUX_DATA_BUS_WIDTH_16) && \
    (BSP_GPIO_MUX_DATA_BUS_WIDTH != BSP_GPIO_MUX_DATA_BUS_WIDTH_32) 
#error Invalid data bus width
#endif






/*ad*
 * The NS9210 is a 177-pin version of the NS9215.  It has 50 pins that are
 * multiplexed with various functions including GPIO functionality.
 * These pins can be rapidly configured using the definitions in this file.  
 * The functions multiplexed on the 9210 include 4 UARTs, 16 or 32-bit data bus,
 * one SPI bus, one I2C bus, Quadrature Decoder, 4 external interrupts, 
 * 2 external DMA channels, 4 timers with extended PWM I/O pins, Ethernet 
 * MII, CS0, and reset_done.  Of these, the following can be used when the NS9210
 * is mounted on the NS7520 development board:  2 UARTs, 4 External Interrupts,
 * the I2C bus, and 4 timers with extended PWM I/O.
 *
 * By selecting options other than @link BSP_GPIO_MUX_INTERNAL_USE_ONLY , groups 
 * of pins can be defined, setup and programmed at system startup.  An 
 * example of a multiplexer group is @link BSP_GPIO_MUX_SPI , which can be 
 * assigned the following possible 
 * values: @link BSP_GPIO_MUX_INTERNAL_USE_ONLY , @link BSP_GPIO_MUX_USE_PRIMARY_PATH , 
 * or @link BSP_GPIO_MUX_USE_ALTERNATE_PATH .  
 *
 * When @link BSP_GPIO_MUX_SPI_0 is set to @link BSP_GPIO_MUX_USE_PRIMARY_PATH , the 
 * multiplexing will be routed using the primary connection, as
 * defined in the MUX section of the NS9210 Hardware Reference Manual.
 *
 * Alternatively, the group can be set to @link BSP_GPIO_MUX_USE_ALTERNATE_PATH ,
 * which also sets multiplexer pins to use SPI, however the alternate 
 * paths are used inplace of the primary paths.  The NS9210 Hardware 
 * Reference Manual describes the pins that have alternate and primary
 * functions.  Lastly, when @link BSP_GPIO_MUX_SPI_0  is set 
 * to @link BSP_GPIO_MUX_INTERNAL_USE_ONLY , the multiplexer does not route the
 * pins to SPI.  Instead, the pins are available to some other 
 * multiplexing functions, or, if all functions are using 
 * the @link BSP_GPIO_MUX_INTERNAL_USE_ONLY , the pin can be used as a GPIO.
 *
 * Also included are GPIO access functions for setting and sensing the 
 * state of the pins.  See @link NAgetGPIOpin and @link NAsetGPIOpin for more
 * details.
 *
 *
 * @note Only one multiplexer group can claim the functionlity on a pin.  If
 * multiple groups claim use on a pin, a compile time error will occur.  This
 * should save time when configuring a BSP.
 *
 * When a multiplexer pin is left unspecified, it defaults to a GPIO
 * receiver.  That means all possible functions that can be routed out a 
 * multiplexer pin have been assigned the BSP_GPIO_MUX_INTERNAL_USE_ONLY 
 * setting.
 *
 * To change a multiplexer pin to a GPIO output, see the section on
 * "Altering the BSP_GPIO_INITIAL_STATE_PINx".  For convenience, all 50 
 * pins have been included.  However, only pins that specify a GPIO output
 * are necessary.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO
 * @overview Signal Multiplexing and GPIO
*ad*/




/*ad*
 * The NS9210 has the ability to multiplex four IRQ signals to trigger the
 * fast call to interrupt service routines.  Routing of these signals 
 * can use a primary path or alternate.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ
 * @overview IRQ
*ad*/

/*ad*
 * This directive controls how the IRQ0 signal is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary or 
 * 3 alternate GPIO pins.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
 * @see @link BSP_GPIO_MUX_USE_2ND_ALTERNATE_PATH
 * @see @link BSP_GPIO_MUX_USE_3RD_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IRQ_0                          BSP_GPIO_MUX_INTERNAL_USE_ONLY


/*ad*
 * This directive controls how the IRQ1 signal is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary or 
 * 2 alternate GPIO pins.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
 * @see @link BSP_GPIO_MUX_USE_2ND_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IRQ_1                          BSP_GPIO_MUX_INTERNAL_USE_ONLY


/*ad*
 * This directive controls how the IRQ2 signal is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary or 
 * 2 alternate GPIO pins.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IRQ_2                          BSP_GPIO_MUX_INTERNAL_USE_ONLY


/*ad*
 * This directive controls how the IRQ3 signal is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the one pin.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_IRQ_3                          BSP_GPIO_MUX_INTERNAL_USE_ONLY



/*
 * This directive controls how the IRQ0 signal is configured.
 * It can be configured to be an active high or active low 
 * level sensitive interrupt, or a rising or falling edge
 * sensitive interrupt.
 *
 * @note    This directive is ignored if BSP_GPIO_MUX_IRQ_0
 *          is set to BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ:IRQ9750_9360
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_LOW
 * @see @link BSP_GPIO_MUX_IRQ_RISING_EDGE
 * @see @link BSP_GPIO_MUX_IRQ_FALLING_EDGE
 */
#define BSP_GPIO_MUX_IRQ_0_CONFIG BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
#if (BSP_GPIO_MUX_IRQ_0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #if (BSP_GPIO_MUX_IRQ_0_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_HIGH) && \
        (BSP_GPIO_MUX_IRQ_0_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_LOW) && \
        (BSP_GPIO_MUX_IRQ_0_CONFIG != BSP_GPIO_MUX_IRQ_RISING_EDGE) && \
        (BSP_GPIO_MUX_IRQ_0_CONFIG != BSP_GPIO_MUX_IRQ_FALLING_EDGE) 
        #error BSP_GPIO_MUX_IRQ_0 is not set correctly.
    #endif
#endif

/*
 * This directive controls how the IRQ1 signal is configured.
 * It can be configured to be an active high or active low 
 * level sensitive interrupt, or a rising or falling edge
 * sensitive interrupt.
 *
 * @note    This directive is ignored if BSP_GPIO_MUX_IRQ_1
 *          is set to BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ:IRQ9750_9360
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_LOW
 * @see @link BSP_GPIO_MUX_IRQ_RISING_EDGE
 * @see @link BSP_GPIO_MUX_IRQ_FALLING_EDGE
 */
#define BSP_GPIO_MUX_IRQ_1_CONFIG BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
#if (BSP_GPIO_MUX_IRQ_1 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #if (BSP_GPIO_MUX_IRQ_1_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_HIGH) && \
        (BSP_GPIO_MUX_IRQ_1_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_LOW) && \
        (BSP_GPIO_MUX_IRQ_1_CONFIG != BSP_GPIO_MUX_IRQ_RISING_EDGE) && \
        (BSP_GPIO_MUX_IRQ_1_CONFIG != BSP_GPIO_MUX_IRQ_FALLING_EDGE) 
        #error BSP_GPIO_MUX_IRQ_1 is not set correctly.
    #endif
#endif


/*
 * This directive controls how the IRQ2 signal is configured.
 * It can be configured to be an active high or active low 
 * level sensitive interrupt, or a rising or falling edge
 * sensitive interrupt.
 *
 * @note    This directive is ignored if BSP_GPIO_MUX_IRQ_2
 *          is set to BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ:IRQ9750_9360
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_LOW
 * @see @link BSP_GPIO_MUX_IRQ_RISING_EDGE
 * @see @link BSP_GPIO_MUX_IRQ_FALLING_EDGE
 */
#define BSP_GPIO_MUX_IRQ_2_CONFIG BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
#if (BSP_GPIO_MUX_IRQ_2 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #if (BSP_GPIO_MUX_IRQ_2_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_HIGH) && \
        (BSP_GPIO_MUX_IRQ_2_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_LOW) && \
        (BSP_GPIO_MUX_IRQ_2_CONFIG != BSP_GPIO_MUX_IRQ_RISING_EDGE) && \
        (BSP_GPIO_MUX_IRQ_2_CONFIG != BSP_GPIO_MUX_IRQ_FALLING_EDGE) 
        #error BSP_GPIO_MUX_IRQ_2 is not set correctly.
    #endif
#endif


/*
 * This directive controls how the IRQ3 signal is configured.
 * It can be configured to be an active high or active low 
 * level sensitive interrupt, or a rising or falling edge
 * sensitive interrupt.
 *
 * @note    This directive is ignored if BSP_GPIO_MUX_IRQ_3
 *          is set to BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:IRQ:IRQ9750_9360
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
 * @see @link BSP_GPIO_MUX_IRQ_ACTIVE_LOW
 * @see @link BSP_GPIO_MUX_IRQ_RISING_EDGE
 * @see @link BSP_GPIO_MUX_IRQ_FALLING_EDGE
 */
#define BSP_GPIO_MUX_IRQ_3_CONFIG BSP_GPIO_MUX_IRQ_ACTIVE_HIGH
#if (BSP_GPIO_MUX_IRQ_3 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #if (BSP_GPIO_MUX_IRQ_3_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_HIGH) && \
        (BSP_GPIO_MUX_IRQ_3_CONFIG != BSP_GPIO_MUX_IRQ_ACTIVE_LOW) && \
        (BSP_GPIO_MUX_IRQ_3_CONFIG != BSP_GPIO_MUX_IRQ_RISING_EDGE) && \
        (BSP_GPIO_MUX_IRQ_3_CONFIG != BSP_GPIO_MUX_IRQ_FALLING_EDGE) 
        #error BSP_GPIO_MUX_IRQ_3 is not set correctly.
    #endif
#endif



/*ad*
 * The NS9210 can support one Serial Peripheral Interface (SPI) bus.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SPI
 * @overview SPI
*ad*/

/*ad*
 * This directive controls how the SPI bus is routed through
 * the GPIO multiplexor.  
 * These signals can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary or 
 * alternate GPIO pins.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SPI
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_SPI_0                          BSP_GPIO_MUX_INTERNAL_USE_ONLY

#if (BSP_GPIO_MUX_SPI_0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error The SPI bus cannot be configured using gpio.h on this module. 
    #error Please refer to the SPI master or slave example applications on how to configure it.
#endif

/*ad*
 * The NS9210 has the ability to multiplex the 2 DMA channels.  These  
 * channels are used to transfer data to (and from) memory space to 
 * an external peripheral.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:DMA
 * @overview DMA
*ad*/

/*ad*
 * This directive controls whether the external DMA channel 0 
 * signals are routed out the GPIO multiplexer.  These signals 
 * can stay internal (allowing GPIO or other special functions 
 * to multiplex), or can be routed to the primary or alternate 
 * GPIO pins.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:DMA
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_DMA_0                          BSP_GPIO_MUX_INTERNAL_USE_ONLY

#if (BSP_GPIO_MUX_DMA_0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error The Digi International NS7520 development board does not support
    #error external DMA.  However, this is not necessarily true
    #error on your board.  Please consult with the hardware designer
    #error of your board.
#endif


/*ad*
 * This directive controls how the external DMA channel 1 
 * signals are routed out the GPIO multiplexer.  These signals 
 * can stay internal (allowing GPIO or other special functions 
 * to multiplex), or can be routed to the primary or alternate 
 * GPIO pins.  
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:DMA
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_DMA_1                          BSP_GPIO_MUX_INTERNAL_USE_ONLY

#if (BSP_GPIO_MUX_DMA_1 != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error The Digi International NS7520 development board does not support
    #error external DMA.  However, this is not necessarily true
    #error on your board.  Please consult with the hardware designer
    #error of your board.
#endif





/*ad*
 * The physical I2C bus consists of two open-drain signal lines: serial 
 * data (SDA) and serial clock (SCL). Pullup resistors are required; see 
 * the standard I2C bus specification for the correct value for the 
 * application. Each device connected to the bus is software addressable
 * by a unique 7- or 10-bit address, and a simple master/slave relationship
 * exists at all times.
 *
 * The internal NS9210 GPIO/Multiplexer has two optional ports to switch 
 * the two I2C lines: a primary and alternate connection.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:I2C
 * @overview I2C
*ad*/

/*ad*
 * This directive controls how the I2C is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary or 
 * alternate GPIO pin.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:I2C
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_I2C                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_I2C != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_I2C != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_I2C != BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Invalid I2C configuration
#endif




/*ad*
 * NS9210 has one Quadrature Decoder/Coder.  It is used to determine the direction
 * and rate of rotation of a wheel such as an electric motor or a control knob.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:QDC
 * @overview Quadrature Decoder/Coder
*ad*/

/*ad*
 * This directive controls how the quadrature decoder/coder is multiplexed.
 * These signals can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary GPIO pins.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:QDC
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_QDC                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_QDC != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_QDC != BSP_GPIO_MUX_USE_PRIMARY_PATH) 
#error Invalid QDC configuration
#endif

#if (BSP_GPIO_MUX_QDC != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error This module does not support a quadrature
#endif




/*ad*
 * NS9210 can be configured to support a reset_done signal.  The reset_done
 * signal is asserted when the processor comes out of reset.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:RESET_OUT
 * @overview Reset Out Signal
*ad*/

/*ad*
 * This directive controls how the reset_done signal is multiplexed.
 * This signal can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary,
 * or alternate GPIO pin.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:RESET_DONE
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_RESET_DONE                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_RESET_DONE != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_RESET_DONE != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_RESET_DONE != BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Invalid QDC configuration
#endif




/*ad*
 * The NS9210 can emulate the CS0 functionality of the NS7520.  
 * Two GPIO pins are used to generate the signals CS0OE_ and 
 * CS0WE_.  When this feature is enabled, the signals are used
 * to maximize the read access timing for external memory 
 * peripherals attached to CS0.  Refer to the Hardware
 * Reference manuals for the NS9210, NS9215, and NS7520 for
 * details.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:CS0
 * @overview Chip Select 0
*ad*/

/*ad*
 * This directive controls how the CS0 signals CS0OE_ and CS0WE_ are multiplexed.
 * These signals can stay internal (allowing GPIO or other special 
 * functions to multiplex) or can be routed to the primary GPIO pins.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:CS0
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_CS0                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_CS0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_CS0 != BSP_GPIO_MUX_USE_PRIMARY_PATH) 
#error Invalid QDC configuration
#endif




/*ad*
 * The NS9210 has 10 timers.  Timers 5 - 9 have I/O pins which are routed through
 * the GPIP multiplexer.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @overview Timer
*ad*/


/*ad*
 * This directive controls how the Timer 5 input signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_5_INPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_5 == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 5 is not available on the alternate path
#endif

/*ad*
 * This directive controls how the Timer 5 output signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_5_OUTPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_5_OUTPUT == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 5 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 6 input signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_6_INPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_6_INPUT == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 6 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 6 output signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_6_OUTPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_6_OUTPUT == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 6 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 7 input signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_7_INPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_7 == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 7 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 7 output signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_7_OUTPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_7 == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 7 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 8 input signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_8_INPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_8_INPUT == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 8 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 8 output signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_8_OUTPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_8_OUTPUT == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 8 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 9 input signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_9_INPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_9 == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 9 is not available on the alternate path
#endif


/*ad*
 * This directive controls how the Timer 9 output signal is routed
 * through the GPIO multiplexer.  This signal can stay internal 
 * (allowing GPIO or other special functions to multiplex), or 
 * can be routed to the primary GPIO pin.
 *
 * Note this function has no alternate path available through 
 * the GPIO multiplexer
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:Timer
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_TIMER_9_OUTPUT                        BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_TIMER_9 == BSP_GPIO_MUX_USE_ALTERNATE_PATH)
#error Timer 9 is not available on the alternate path
#endif








/*ad*
 * The NS9210 contains 4 serial channels that can be multiplexed.  Only ports
 * A and C are available on the NS7520 development board.  These  
 * channels can be wired according to the type of serial 
 * communication needed. 
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface
 * @overview Serial
*ad*/

/*ad*
 * The NS9210 on the NS7520 development board has 2 serial channels that
 * are routed through the GPIO multiplexer.
 * 
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface:SerialChannels
 * @overview Channels
*ad*/



/*ad*
 * This directive controls how Serial Port A is multiplexed.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins based on the particular serial configuration.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface:SerialChannels
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_SERIAL_2_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_4_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_6_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_8_WIRE_UART
*ad*/
#define BSP_GPIO_MUX_SERIAL_A                           BSP_GPIO_MUX_SERIAL_8_WIRE_UART
#if (BSP_GPIO_MUX_SERIAL_A != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_SERIAL_A != BSP_GPIO_MUX_SERIAL_2_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_A != BSP_GPIO_MUX_SERIAL_4_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_A != BSP_GPIO_MUX_SERIAL_6_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_A != BSP_GPIO_MUX_SERIAL_8_WIRE_UART) 
#error Invalid Serial Port A configuration
#endif



/*ad*
 * This directive controls how Serial Port B is multiplexed.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins based on the particular serial configuration.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface:SerialChannels
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_SERIAL_2_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_4_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_6_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_8_WIRE_UART
*ad*/
#define BSP_GPIO_MUX_SERIAL_B                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_SERIAL_2_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_SERIAL_4_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_SERIAL_6_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_SERIAL_8_WIRE_UART) 
#error Invalid Serial Port B configuration
#endif

#if (BSP_GPIO_MUX_SERIAL_B != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error The Digi International NS7520 development board does not support
    #error serial port B.  However, this is not necessarily true
    #error on your board.  Please consult with the hardware designer
    #error of your board.
#endif




/*ad*
 * This directive controls how Serial Port C is multiplexed.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins based on the particular serial configuration.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface:SerialChannels
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_SERIAL_2_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_4_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_6_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_8_WIRE_UART
*ad*/
#define BSP_GPIO_MUX_SERIAL_C                           BSP_GPIO_MUX_SERIAL_2_WIRE_UART
#if (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_SERIAL_2_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_SERIAL_4_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_SERIAL_6_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_SERIAL_8_WIRE_UART) 
#error Invalid Serial Port C configuration
#endif

#if ((BSP_GPIO_MUX_SERIAL_C == BSP_GPIO_MUX_SERIAL_8_WIRE_UART) || \
    (BSP_GPIO_MUX_SERIAL_C != BSP_GPIO_MUX_SERIAL_4_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_C == BSP_GPIO_MUX_SERIAL_6_WIRE_UART))
    #error This module does not support more than 2 wires on port C
#endif





/*ad*
 * This directive controls how Serial Port D is multiplexed.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins based on the particular serial configuration.
 *
 * @note Serial Port D can't be used as BSP_GPIO_MUX_SERIAL_8_WIRE_UART.
 * The limitation is imposed by ASIC bug: GPIO28 should be configured 
 * as same as GPIO29, which is the RTS line for Serial Port D, and the Ring indicator 
 * won't work. When Serial Port D is used as BSP_GPIO_MUX_SERIAL_4_WIRE_UART or
 * BSP_GPIO_MUX_SERIAL_6_WIRE_UART, GPIO28 should be configured 
 * as same as GPIO29, which is the RTS line for Serial Port D, GPIO28 should not be 
 * used as other functions.
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:SerialInterface:SerialChannels
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_SERIAL_2_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_4_WIRE_UART
 * @see @link BSP_GPIO_MUX_SERIAL_6_WIRE_UART
*ad*/
#define BSP_GPIO_MUX_SERIAL_D                          BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_SERIAL_D != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_SERIAL_D != BSP_GPIO_MUX_SERIAL_2_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_D != BSP_GPIO_MUX_SERIAL_4_WIRE_UART) && \
    (BSP_GPIO_MUX_SERIAL_D != BSP_GPIO_MUX_SERIAL_6_WIRE_UART)
#error Invalid Serial Port C configuration
#endif

#if (BSP_GPIO_MUX_SERIAL_D != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
    #error The Digi International NS7520 development board does not support
    #error serial port D.  However, this is not necessarily true
    #error on your board.  Please consult with the hardware designer
    #error of your board.
#endif




/*ad*
 * This directive controls how Ethernet is configured.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins based on the particular serial configuration.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:Ethernet
 * @see @link BSP_GPIO_MUX_ETHERNET_MII
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
*ad*/

#define BSP_GPIO_MUX_ETHERNET_PHY_INTERFACE    BSP_GPIO_MUX_ETHERNET_MII
#if (BSP_GPIO_MUX_ETHERNET_PHY_INTERFACE != BSP_GPIO_MUX_ETHERNET_MII) && \
    (BSP_GPIO_MUX_ETHERNET_PHY_INTERFACE != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
#error Invalid Ethernet PHY Interface configuration
#endif

#if (BSP_GPIO_MUX_ETHERNET_PHY_INTERFACE != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
/*ad*
 * This directive controls how the Ethernet PHY TXER signal is multiplexed.
 * This signal is often not implemented on certain low cost MII PHYs.
 *
 * The signals can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.
 *
 * The Primary path will route the internal Ethernet module to the external 
 * PHY.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:Ethernet
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_ETHERNET_PHY_TXER                BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_ETHERNET_PHY_TXER != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_ETHERNET_PHY_TXER != BSP_GPIO_MUX_USE_PRIMARY_PATH)
#error Invalid Ethernet PHY TXER configuration
#endif

/*ad*
 * This directive controls how the Ethernet PHY RXER signal is multiplexed.
 * This signal is often not implemented on certain low cost MII PHYs.
 *
 * The signals can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * The Primary path will route the internal Ethernet module to the external 
 * PHY.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:Ethernet
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_ETHERNET_PHY_RXER                BSP_GPIO_MUX_USE_PRIMARY_PATH
#if (BSP_GPIO_MUX_ETHERNET_PHY_RXER != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_ETHERNET_PHY_RXER != BSP_GPIO_MUX_USE_PRIMARY_PATH)
#error Invalid Ethernet PHY RXER configuration
#endif

#else /* if Ethernet interface disabled */
    #define BSP_GPIO_MUX_ETHERNET_PHY_TXER      BSP_GPIO_MUX_INTERNAL_USE_ONLY
    #define BSP_GPIO_MUX_ETHERNET_PHY_RXER      BSP_GPIO_MUX_INTERNAL_USE_ONLY
#endif



/*ad*
 * This directive controls how general I/O signal 0 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_0             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_0 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_0 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_0
#endif



/*ad*
 * This directive controls how general I/O signal 1 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_1             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_1 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_1 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_1 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_1
#endif



/*ad*
 * This directive controls how general I/O signal 2 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_2             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_2 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_2 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_2 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_2
#endif


/*ad*
 * This directive controls how general I/O signal 3 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_3             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_3 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_3 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_3 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_3
#endif


/*ad*
 * This directive controls how general I/O signal 4 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_4             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_4 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_4 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_4
#endif



/*ad*
 * This directive controls how general I/O signal 5 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_5             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_5 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_5 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_5
#endif



/*ad*
 * This directive controls how general I/O signal 6 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_6             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_6 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_6 != BSP_GPIO_MUX_USE_ALTERNATE_PATH)  
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_6
#endif


/*ad*
 * This directive controls how general I/O signal 7 for I/O processor 0 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_GEN_IO_7             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_GEN_IO_7 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_0_GEN_IO_7 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_GEN_IO_7
#endif



/*ad*
 * This directive controls how the CAN receive signal on I/O processor 0
 * is routed through the GPIO multiplexer
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_CAN_RXD              BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_CAN_RXD != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_CAN_RXD
#endif


/*ad*
 * This directive controls how the CAN transmit signal on I/O processor 0
 * is routed through the GPIO multiplexer
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_0_CAN_TXD              BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_0_CAN_TXD != BSP_GPIO_MUX_INTERNAL_USE_ONLY)
#error Invalid configuration for BSP_GPIO_MUX_IOP_0_CAN_TXD
#endif

/*ad*
 * This directive controls how general I/O signal 0 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_0             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_0 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_0 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_0 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_0
#endif



/*ad*
 * This directive controls how general I/O signal 1 for I/O processor 1
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_1             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_1 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_1 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_1 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_1
#endif



/*ad*
 * This directive controls how general I/O signal 2 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_2             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_2 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_2 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_2 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_2
#endif


/*ad*
 * This directive controls how general I/O signal 3 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_3             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_3 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_3 != BSP_GPIO_MUX_USE_PRIMARY_PATH) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_3 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_3
#endif



/*ad*
 * This directive controls how general I/O signal 4 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_4             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_4 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_4 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_4
#endif



/*ad*
 * This directive controls how general I/O signal 5 for I/O processor 1
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_5             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_5 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_5 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_5
#endif



/*ad*
 * This directive controls how general I/O signal 6 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_6             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_6 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_6 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_6
#endif


/*ad*
 * This directive controls how general I/O signal 7 for I/O processor 1 
 * is multiplexed.
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ALTERNATE_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_GEN_IO_7             BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_GEN_IO_7 != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_GEN_IO_7 != BSP_GPIO_MUX_USE_ALTERNATE_PATH) 
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_GEN_IO_7
#endif


/*ad*
 * This directive controls how the CAN receive signal on I/O processor 1
 * is routed through the GPIO multiplexer
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_CAN_RXD              BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_CAN_RXD != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_CAN_RXD != BSP_GPIO_MUX_USE_PRIMARY_PATH)
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_CAN_RXD
#endif


/*ad*
 * This directive controls how the CAN transmit signal on I/O processor 1
 * is routed through the GPIO multiplexer
 *
 * The signal can stay internal (allowing GPIO or other special functions 
 * to multiplex) or can be routed out to the GPIO pin.  
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:IOP
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_PRIMARY_PATH
*ad*/
#define BSP_GPIO_MUX_IOP_1_CAN_TXD              BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_IOP_1_CAN_TXD != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_IOP_1_CAN_TXD != BSP_GPIO_MUX_USE_PRIMARY_PATH)
#error Invalid configuration for BSP_GPIO_MUX_IOP_1_CAN_RXD
#endif


/*ad*
 * This directive controls high order address memory.
 * The signals can stay internal (allowing GPIO or other 
 * special functions to multiplex) or can be routed to GPIO 
 * pins.
 *
 * @since 6.2
 * @external
 * @category Mux_and_GPIO:Memory
 * @see @link BSP_GPIO_MUX_INTERNAL_USE_ONLY
 * @see @link BSP_GPIO_MUX_USE_ADDR_BIT_24
 * @see @link BSP_GPIO_MUX_USE_ADDR_BIT_25_AND_LOWER
 * @see @link BSP_GPIO_MUX_USE_ADDR_BIT_26_AND_LOWER
 * @see @link BSP_GPIO_MUX_USE_ADDR_BIT_27_AND_LOWER
*ad*/
#define BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING  BSP_GPIO_MUX_INTERNAL_USE_ONLY
#if (BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING != BSP_GPIO_MUX_INTERNAL_USE_ONLY) && \
    (BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING != BSP_GPIO_MUX_USE_ADDR_BIT_24) && \
    (BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING != BSP_GPIO_MUX_USE_ADDR_BIT_25_AND_LOWER) && \
    (BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING != BSP_GPIO_MUX_USE_ADDR_BIT_26_AND_LOWER) && \
    (BSP_GPIO_MUX_HIGH_ORDER_ADDRESSING != BSP_GPIO_MUX_USE_ADDR_BIT_27_AND_LOWER) 
#error Invalid High Order Memory Address configuration
#endif


/*ad*
 * Discrete signals can be controlled or sensed using a General Purpose 
 * Input/Output (GPIO) pin.  This pin is able to drive logic or read 
 * levels.  This functionality is available on all Signal Multiplexed pins.
 *
 * When a MUX pin is not configured (to a serial, or Timer, etc), then
 * the functionality defaults to GPIO.  In other words, to setup a pin
 * to have GPIO functionality, all of the associated multiplexer groups 
 * must be defined as BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * When the MUX pin is set to GPIO, three initial states are available:
 * one for receiver, one for a driver initially set to logic 0, and
 * another for a driver set to logic 1.
 *
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:GPIOInterface
 * @overview GPIO
*ad*/

/*ad*
 * Altering the BSP_GPIO_INITIAL_STATE_PINx
 *
 * The following BSP_GPIO_INITIAL_STATE_PINx directives control the 
 * I/O configuration if and only if the MUX has not been configured
 * to some other available function.  
 *
 * When a MUX pin is not configured (to a serial, or Timer, etc), then
 * the functionality multiplexed is GPIO.  In other words, to setup a pin
 * to have GPIO functionality, all of the associated multiplexer groups 
 * must be defined as BSP_GPIO_MUX_INTERNAL_USE_ONLY.
 *
 * Addtionally, if the MUX is configured to use something other than the 
 * GPIO functionality, then the definitions below will be ignored on that 
 * particalur multiplexer pin.
 *
 * When the MUX pin is set to GPIO, three initial states are available:
 * one for receiver, one for a driver initially set to logic 0, and
 * another for a driver set to logic 1.
 *
 * @name GPIO_INITIAL_STATE_PINx "GPIO Initial Pin State"
 *
 * @note The safe setting for this is BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER,
 * which programs the pin to a receive configuration.
 *
 * @param BSP_GPIO_INITIAL_STATE_PIN0  "Initial state of GPIO pin 0" 
 * @param BSP_GPIO_INITIAL_STATE_PIN1  "Initial state of GPIO pin 1" 
 * @param BSP_GPIO_INITIAL_STATE_PIN2  "Initial state of GPIO pin 2" 
 * @param BSP_GPIO_INITIAL_STATE_PIN3  "Initial state of GPIO pin 3" 
 * @param BSP_GPIO_INITIAL_STATE_PIN4  "Initial state of GPIO pin 4" 
 * @param BSP_GPIO_INITIAL_STATE_PIN5  "Initial state of GPIO pin 5" 
 * @param BSP_GPIO_INITIAL_STATE_PIN6  "Initial state of GPIO pin 6" 
 * @param BSP_GPIO_INITIAL_STATE_PIN7  "Initial state of GPIO pin 7" 
 * @param BSP_GPIO_INITIAL_STATE_PIN8  "Initial state of GPIO pin 8" 
 * @param BSP_GPIO_INITIAL_STATE_PIN9  "Initial state of GPIO pin 9" 
 * @param BSP_GPIO_INITIAL_STATE_PIN10  "Initial state of GPIO pin 10" 
 * @param BSP_GPIO_INITIAL_STATE_PIN11  "Initial state of GPIO pin 11" 
 * @param BSP_GPIO_INITIAL_STATE_PIN12  "Initial state of GPIO pin 12" 
 * @param BSP_GPIO_INITIAL_STATE_PIN13  "Initial state of GPIO pin 13" 
 * @param BSP_GPIO_INITIAL_STATE_PIN14  "Initial state of GPIO pin 14" 
 * @param BSP_GPIO_INITIAL_STATE_PIN15  "Initial state of GPIO pin 15" 
 * @param BSP_GPIO_INITIAL_STATE_PIN16  "Initial state of GPIO pin 16" 
 * @param BSP_GPIO_INITIAL_STATE_PIN17  "Initial state of GPIO pin 17" 
 * @param BSP_GPIO_INITIAL_STATE_PIN18  "Initial state of GPIO pin 18" 
 * @param BSP_GPIO_INITIAL_STATE_PIN19  "Initial state of GPIO pin 19" 
 * @param BSP_GPIO_INITIAL_STATE_PIN20  "Initial state of GPIO pin 20" 
 * @param BSP_GPIO_INITIAL_STATE_PIN21  "Initial state of GPIO pin 21" 
 * @param BSP_GPIO_INITIAL_STATE_PIN22  "Initial state of GPIO pin 22" 
 * @param BSP_GPIO_INITIAL_STATE_PIN23  "Initial state of GPIO pin 23" 
 * @param BSP_GPIO_INITIAL_STATE_PIN24  "Initial state of GPIO pin 24" 
 * @param BSP_GPIO_INITIAL_STATE_PIN25  "Initial state of GPIO pin 25" 
 * @param BSP_GPIO_INITIAL_STATE_PIN26  "Initial state of GPIO pin 26" 
 * @param BSP_GPIO_INITIAL_STATE_PIN27  "Initial state of GPIO pin 27" 
 * @param BSP_GPIO_INITIAL_STATE_PIN28  "Initial state of GPIO pin 28" 
 * @param BSP_GPIO_INITIAL_STATE_PIN29  "Initial state of GPIO pin 29" 
 * @param BSP_GPIO_INITIAL_STATE_PIN30  "Initial state of GPIO pin 30" 
 * @param BSP_GPIO_INITIAL_STATE_PIN31  "Initial state of GPIO pin 31" 
 * @param BSP_GPIO_INITIAL_STATE_PIN32  "Initial state of GPIO pin 32" 
 * @param BSP_GPIO_INITIAL_STATE_PIN33  "Initial state of GPIO pin 33" 
 * @param BSP_GPIO_INITIAL_STATE_PIN34  "Initial state of GPIO pin 34" 
 * @param BSP_GPIO_INITIAL_STATE_PIN35  "Initial state of GPIO pin 35" 
 * @param BSP_GPIO_INITIAL_STATE_PIN36  "Initial state of GPIO pin 36" 
 * @param BSP_GPIO_INITIAL_STATE_PIN37  "Initial state of GPIO pin 37" 
 * @param BSP_GPIO_INITIAL_STATE_PIN38  "Initial state of GPIO pin 38" 
 * @param BSP_GPIO_INITIAL_STATE_PIN39  "Initial state of GPIO pin 39" 
 * @param BSP_GPIO_INITIAL_STATE_PIN40  "Initial state of GPIO pin 40" 
 * @param BSP_GPIO_INITIAL_STATE_PIN41  "Initial state of GPIO pin 41" 
 * @param BSP_GPIO_INITIAL_STATE_PIN42  "Initial state of GPIO pin 42" 
 * @param BSP_GPIO_INITIAL_STATE_PIN43  "Initial state of GPIO pin 43" 
 * @param BSP_GPIO_INITIAL_STATE_PIN44  "Initial state of GPIO pin 44" 
 * @param BSP_GPIO_INITIAL_STATE_PIN45  "Initial state of GPIO pin 45" 
 * @param BSP_GPIO_INITIAL_STATE_PIN46  "Initial state of GPIO pin 46" 
 * @param BSP_GPIO_INITIAL_STATE_PIN47  "Initial state of GPIO pin 47" 
 * @param BSP_GPIO_INITIAL_STATE_PIN48  "Initial state of GPIO pin 48" 
 * @param BSP_GPIO_INITIAL_STATE_PIN49  "Initial state of GPIO pin 49" 
 *
 * @since 6.1
 * @external
 * @category Mux_and_GPIO:GPIOInterface
 * @see @link BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC0
 * @see @link BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC1
 * @see @link BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
*ad*/
#define BSP_GPIO_INITIAL_STATE_PIN0                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN1                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN2                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN3                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN4                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN5                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN6                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN7                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN8                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN9                 BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN10                BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC0
#define BSP_GPIO_INITIAL_STATE_PIN11                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN12                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN13                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN14                BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC0
#define BSP_GPIO_INITIAL_STATE_PIN15                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN16                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN17                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN18                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN19                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN20                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN21                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN22                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN23                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN24                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN25                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN26                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN27                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN28                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN29                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN30                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN31                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN32                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN33                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN34                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN35                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN36                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN37                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN38                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN39                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN40                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN41                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN42                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN43                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN44                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN45                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN46                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN47                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN48                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PIN49                BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER

#define BSP_GPIO_INITIAL_STATE_PINA24               BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PINA25               BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PINA26               BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
#define BSP_GPIO_INITIAL_STATE_PINA27               BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER



/*
 * The GPIO pins on the NS9215 have internal pullup resisters.  These can be enabled 
 * or disabled for each pin.
 *
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:GPIO9215:Pullups
 * @overview GPIO
 * @include <gpio.h>
 * @library bsp
 * @platform all
 */

/*
 * These constant control the settings for the internal pullup resisters on each
 * GPIO pin.  Set a constant to TRUE to enable the pullup, or to FALSE to disable
 * the pullup.
 *
 * @name GPIO_PULLUP_PINx "GPIO Pullup Enable/Disable"
 *                 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN0  "Configures pullup on pin 0" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN1  "Configures pullup on pin 1" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN2  "Configures pullup on pin 2" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN3  "Configures pullup on pin 3" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN4  "Configures pullup on pin 4" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN5  "Configures pullup on pin 5" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN6  "Configures pullup on pin 6" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN7  "Configures pullup on pin 7" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN8  "Configures pullup on pin 8" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN9  "Configures pullup on pin 9" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN10  "Configures pullup on pin 10" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN11  "Configures pullup on pin 11" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN12  "Configures pullup on pin 12" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN13  "Configures pullup on pin 13" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN14  "Configures pullup on pin 14" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN15  "Configures pullup on pin 15" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN16  "Configures pullup on pin 16" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN17  "Configures pullup on pin 17" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN18  "Configures pullup on pin 18" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN19  "Configures pullup on pin 19" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN20  "Configures pullup on pin 20" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN21  "Configures pullup on pin 21" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN22  "Configures pullup on pin 22" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN23  "Configures pullup on pin 23" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN24  "Configures pullup on pin 24" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN25  "Configures pullup on pin 25" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN26  "Configures pullup on pin 26" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN27  "Configures pullup on pin 27" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN28  "Configures pullup on pin 28" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN29  "Configures pullup on pin 29" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN30  "Configures pullup on pin 30" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN31  "Configures pullup on pin 31" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN32  "Configures pullup on pin 32" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN33  "Configures pullup on pin 33" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN34  "Configures pullup on pin 34" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN35  "Configures pullup on pin 35" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN36  "Configures pullup on pin 36" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN37  "Configures pullup on pin 37" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN38  "Configures pullup on pin 38" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN39  "Configures pullup on pin 39" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN40  "Configures pullup on pin 40" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN41  "Configures pullup on pin 41" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN42  "Configures pullup on pin 42" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN43  "Configures pullup on pin 43" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN44  "Configures pullup on pin 44" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN45  "Configures pullup on pin 45" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN46  "Configures pullup on pin 46" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN47  "Configures pullup on pin 47" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN48  "Configures pullup on pin 48" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PIN49  "Configures pullup on pin 49" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PINA24  "Configures pullup on pin A24" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PINA25  "Configures pullup on pin A25" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PINA26  "Configures pullup on pin A26" 
 * @param BSP_GPIO_ENABLE_PULLUP_ON_PINA27  "Configures pullup on pin A27" 
 *
 * @since 7.3
 * @external
 * @category BSP:Device_Drivers:Mux_and_GPIO:GPIO9215:Pullups
 * @see @link BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC0
 * @see @link BSP_GPIO_INITIAL_STATE_OUTPUT_DRIVER_LOGIC1
 * @see @link BSP_GPIO_INITIAL_STATE_INPUT_RECEIVER
 */
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN0                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN1                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN2                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN3                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN4                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN5                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN6                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN7                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN8                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN9                 TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN10                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN11                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN12                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN13                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN14                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN15                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN16                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN17                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN18                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN19                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN20                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN21                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN22                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN23                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN24                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN25                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN26                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN27                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN28                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN29                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN30                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN31                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN32                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN33                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN34                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN35                TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN36                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN37                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN38                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN39                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN40                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN41                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN42                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN43                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN44                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN45                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN46                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN47                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN48                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PIN49                FALSE
#define BSP_GPIO_ENABLE_PULLUP_ON_PINA24               TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PINA25               TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PINA26               TRUE
#define BSP_GPIO_ENABLE_PULLUP_ON_PINA27               TRUE


#ifdef __cplusplus
}
#endif


#endif








