/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 *  =======================================================================
 *  This file defines the ROM based (const) chip select initialization table.
 *  The table contains the chip select settings for the NET+ARM development
 *  board, for all Digi International chips supported by NET+OS.
 *
 *  This table can be modified for a customized BSP.  See Settings.h for the
 *  definition of all the NetarmInitData data members.
 *
 *  Edit Date/Ver   Edit Description
 *  =============   ===================================================
 *  PMJ  06/13/01   Removed symbol _BURST.
 *  SW   03/04/02    Remove the use of bit field
 *  ECL  05/06/02   Added table entry for NETA20M (RevId 19)
 *  JZW  06/02/03   Clean up compiler warnings
 */


#include <sysClock.h>
#include <ncc_init.h>
#include <bsp_arm7refs.h>
#include <bsp_sys.h>
#include <reg_def.h>

#define _NONE                               0
#define _50_1                               0xe1e
#define _50_0                               0xe3e

 
/*ad*
 * NAOptRegWaitAndBurstMask holds the option mask for CS0.  This sets the
 * size of flash ROM.
 *
 * @since 4.0
 * @external
 * @category BSP_Configuration
*ad*/
const unsigned int NAOptRegWaitAndBurstMask   = 0xff0;

/*ad*
 * NAOptRegRsyncMask holds the rsync value for CS0.  This sets the
 * read cycle synchronous mode of the part.
 *
 * @since 4.0
 * @external
 * @category BSP_Configuration
*ad*/
const unsigned int NAOptRegRsyncMask          = 2;

/*ad*
 *      This structure contains the parameters used to initialize the 
 *      unit.  Primarily, these parameters include the system chip 
 *      select settings for Flash (CS0), RAM (CS1) and NVRAM (CS3).  
 *      The NET+OS development board does not use CS4.  The structure
 *      is placed in Flash ROM (via the const keyword) since the data
 *      in it is used prior to System RAM being initialized.  This 
 *      data should remain in ROM.  
 *
 *      This table is indexed by chip
 *      revision IDs.  The revision ID is read from the REV field of
 *      the System Status Register.  See the H/W reference guide for
 *      your NET+ARM chip for details.
 *
 * @since 4.0
 * @external
 * @category BSP_Configuration
 * @see @link NAInitRegisterType
*ad*/
const NAInitRegisterType NANetarmInitData[] =
{
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    /*  RevID - Index  4 (15-0)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index  5 (15-1)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index  6 (15-2)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index  7 (15-3,4)   */
    {1, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index  8 (40-0)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index  9 (40-1)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index 10 (40-2)     */
    {0, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    /*  RevID - Index 11 (40-3,4)   */
    {1, 2, 3, 1, 1, 1, 0, 0, 0, 2, 1, 0, 1, 1, 10},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    /*  RevID - Index 19 (20M)   */
    {1, 4, 0, 0, 0, 0, 1, 1, 2, 2, 1, 0, 1, 1, 12},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    /*  RevID - Index 24 (50-0)     */
    {1, 4, 0, 0, 0, 0, 0, 0, 2, 2, 1, 0, 1, 1, 12},
    /*  RevID - Index 25 (50-1)     */
/**    {1, 4, 0, 0, 0, 0, 1, 1, 2, 2, 1, 0, 1, 1, 12}, **/
       {1, 4, 0, 0, 0, 0, 1, 0, 2, 2, 1, 0, 1, 1, 12},
    /* Future chips */
    {1, 4, 0, 0, 0, 0, 1, 1, 2, 2, 1, 0, 1, 1, 12},
    {1, 4, 0, 0, 0, 0, 1, 1, 2, 2, 1, 0, 1, 1, 12},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
    /*  Index 40    */
    /*  For Connect ME hardware, cs1SdWaitStates can be 1 for highest performance   */
    /*  cs0WaitStates has to be 5 or higher */
    {0 ,               6, 1, 3, 0, 0, 1, 0, 3, 3, 3, 1, 1, 3, 0},
    {BSP_CLOCK_SOURCE, 6, 1, 3, 0, 0, 1, 0, 3, 3, 3, 1, 1, 3, 0},
    {BSP_CLOCK_SOURCE, 6, 1, 3, 0, 0, 1, 0, 3, 3, 3, 1, 1, 3, 0}
};

/*ad*
 * This table lists the PLL settings for different chips.  The table is indexed by
 * the chip revision ID reported in the REV field of the SSR.  The settings in this
 * table are the ones that are written to the PLL by the initialization code
 * in init.s.  This is done for the NET+12, NET+15, NET+20M, and NET+50.  The PLL
 * on the NS7520 is set at power up by hardware, and not changed by software.
 *
 * @external
 * @category BSP_Configuration
 * @since 4.0
*ad*/
const WORD32 NA_PLL_TABLE[] =
{
    0x06000000,         /* rev = 0, NET+5&10                */
    0x06000000,         /* rev = 1, NET+12.1                */
    0x06000000,         /* rev = 2, not used                */
    0x06000000,         /* rev = 3, not used                */
    0x06000000,         /* rev = 4, NET+15.0                */
    0x06000000,         /* rev = 5, NET+15.1                */
    0x06000000,         /* rev = 6, NET+15.2                */
    0x06000000,         /* rev = 7, NET+15.3 and NET+15.4   */
    0x06000000,         /* rev = 8, NET+40.0                */
    0x06000000,         /* rev = 9, NET+40.1                */
    0x06000000,         /* rev = 10, NET+40.2               */
    0x06000000,         /* rev = 11, NET+40.3 and NET+40.4  */
    0x09000e1e,         /* rev = 12, not used               */
    0x09000e1e,         /* rev = 13, not used               */
    0x09000e1e,         /* rev = 14, not used               */
    0x09000e1e,         /* rev = 15, not used               */
    0x09000e1e,         /* rev = 16, NET+20.0               */
    0x09000e1e,         /* rev = 17, NET+20.1               */
    0x09000e1e,         /* rev = 18, NET+20.2               */
    0x09000e1e,         /* rev = 19, NET+20.3               */
    0x09000e1e,         /* rev = 20, not used               */
    0x09000e1e,         /* rev = 21, not used               */
    0x09000e1e,         /* rev = 22, not used               */
    0x09000e1e,         /* rev = 23, not used               */
    0x09000e1e,         /* rev = 24, NET+50.0               */
    0x09000e1e,         /* rev = 25, NET+50.1               */
    0x09000e1e,         /* rev = 26, NET+50.2               */
    0x09000e1e,         /* rev = 27, NET+50.3               */
    0x09000e1e,         /* rev = 28, not used               */
    0x09000e1e,         /* rev = 29, not used               */
    0x09000e1e,         /* rev = 30, not used               */
    0x09000e1e,         /* rev = 31, not used               */
    0x09000e1e,         /* rev = 32, not used               */
    0x09000e1e,         /* rev = 33, not used               */
    0x09000e1e,         /* rev = 34, not used               */
    0x09000e1e,         /* rev = 35, not used               */
    0x09000e1e,         /* rev = 36, not used               */
    0x09000e1e,         /* rev = 37, not used               */
    0x09000e1e,         /* rev = 38, not used               */
    0x09000e1e,         /* rev = 39, not used               */
    0x09000e1e,         /* rev = 40, NS7520.0  PLL set by H/W */
    0x09000e1e,         /* rev = 41, NS7520.1  PLL set by H/W */
    0x09000e1e,         /* rev = 42, NS7520.2  PLL set by H/W */
    0x09000e1e          /* rev = 43, NS7520.3  PLL set by H/W */
};

/*ad*
 *  The NAInterruptPriority array allows flexible prioritization for all 
 *  the NET+ARM interrupts that drive the ARM processor IRQ.  The table 
 *  prioritization requires the lower priority interrupts early in the 
 *  array, and higher priority interrupts towards the end of the array.  
 *  For instance, the NAInterruptPriority array below defaults to using 
 *  bit 0, PORTC PC0, as the systems lowest priority interrupt, and bit 
 *  31, DMA1, as the systems highest priority interrupt.
 *
 *  For example, to alter the system such that PORTC PC0 is inserted as 
 *  the highest priority interrupt, the array should be as follows:
 *
 *  {
 *      1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 14, 13, 15, 
 *      16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0
 *  };
 *
 *  Alternatively, DMA1 can be dropped to the lowest priority interrupt
 *  with the array defined as follows:
 *
 *  {
 *      31, 0, 1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12, 14, 13, 15, 
 *      16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
 *  };
 *
 *  Adjust the values in this array as appropriate for your platform. 
 *  Only priority levels 0-31 are supported, and each level must be used
 *  once and only once.
 *
 *  Warning:    If this list is filled out incorrectly, for example, a 
 *              level is left out, or a level is duplicated, NAInitIsr
 *              will call customizeErrorHandler with ERROR_IRQ_TABLE blinks.
 *
 * @since 4.0
 * @external
 * @category BSP_Configuration
*ad*/
unsigned const NAInterruptPriority[] = 
{
    0,  1,  2,  3,  6,  7,  8,  9,  10, 11, 12, 14, 13, 15, 16, 17, 
    18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,  4,  5
};



/*ad*
 * Return the oscillator type for this chip stored in NANetarmInitData.  The
 * NANetarmInitData array is indexed by the chip ID.  This function
 * reads the chip ID from H/W and uses it to look up the oscillator
 * type stored in the table.
 *
 * @since 4.0
 * @external
 * @category BSP_Configuration
 * @return NA_SELECT_THE_CRYSTAL_INPUT  internal oscillator used
 * @return NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT               external oscillator used
*ad*/
unsigned int NAusesTheInternalOscillator(void)
{
    /*if (NetarmInitData[((*NCC_GEN).ssr.bits.rev)].usesInternalOscillator) */
    int index =narm_read_reg(NARM_GSSR_REG, NARM_GSSR_ADDR, rev);
    
	if (NANetarmInitData[index].usesInternalOscillator)
    {
        return NA_SELECT_THE_CRYSTAL_INPUT;
    }
    else
    {
        return NA_SELECT_THE_EXTERNAL_OSCILLATOR_INPUT;
    }
}



