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> LD rr,(ps+HL) Load Rabbit 4000 Instruction

> Opcode | Instruction | Clocks | Operation
> -- | LD rr,(ps+HL) | 10 (2,2,2,2,2) | rrlow= (ps+d); rrhigh =(ps+d+1)
> 6D 02 | LD BC,(PW+HL) | 10 (2,2,2,2,2) | C = (PW+HL); B = (PW+HL+1)
> 6D 12 | LD BC,(PX+HL) | C = (PX+HL); B = (PX+HL+1)
> 6D 22 | LD BC,(PY+HL) | C = (PY+HL); B = (PY+HL+1)
> 6D 32 | LD BC,(PZ+HL) | C = (PZ+HL); B = (PZ+HL+1)
> 6D 42 | LD DE,(PW+HL) | 10 (2,2,2,2,2) | E = (PW+HL); D = (PW+HL+1)
> 6D 52 | LD DE,(PX+HL) | E = (PX+HL); D = (PX+HL+1)
> 6D 62 | LD DE,(PY+HL) | E = (PY+HL); D = (PY+HL+1)
> 6D 72 | LD DE,(PZ+HL) | E = (PZ+HL); D = (PZ+HL+1)
> 6D 82 | LD IX,(PW+HL) | 10 (2,2,2,2,2) | IXlow=(PW+HL); IXhigh=(PW+HL+1)
> 6D 92 | LD IX,(PX+HL) | IXlow=(PX+HL); IXhigh=(PX+HL+1)
> 6D A2 | LD IX,(PY+HL) | IXlow=(PY+HL); IXhigh=(PY+HL+1)
> 6D B2 | LD IX,(PZ+HL) | IXlow=(PZ+HL); IXhigh=(PZ+HL+1)
> 6D C2 | LD IY,(PW+HL) | 10 (2,2,2,2,2) | IYlow=(PW+HL); IYhigh=(PW+HL+1)
> 6D D2 | LD IY,(PX+HL) | IYlow=(PX+HL); IYhigh=(PX+HL+1)
> 6D E2 | LD IY,(PY+HL) | IYlow=(PY+HL); IYhigh=(PY+HL+1)
> 6D F2 | LD IY,(PZ+HL) | IYlow=(PZ+HL); IYhigh=(PZ+HL+1)

> Flags | ALTD | IOI/IOE
> S | Z | L/V | C | F | R | SP | S | D
> - | - | - | - |  | · |  |  |

> #### Description

> Loads rr (one of the 16-bit registers BC, DE, IX or IY) with the data whose address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

> If ps is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).

> The address is computed as the sum of ps (one of the 32-bit registers PW, PX, PY or PZ) and HL.

> The instructions "LD IX,(ps+d)" and "LD IY,(ps+d)" are not affected by ALTD.

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