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> LD (pd+HL),ps Load Rabbit 4000 Instruction

> Opcode | Instruction | Clocks | Operation
> -- | LD (pd+HL),ps | 18 (2,2,2,3,3,3,3) | (pd+HL)=ps0; (pd+HL+1)=ps1 (pd+HL+2)=ps2; (pd+HL+3)=ps3
> -- 6D 0B 6D 1B 6D 2B 6D 3B | `LD (`pd`+HL),PW` LD (PW+HL),PW LD (PX+HL),PW LD (PY+HL),PW LD (PZ+HL),PW | 18 (2,2,2,3,3,3,3) | (pd+HL)=PW0; (pd+HL+1)=PW1 (pd+HL+2)=PW2; (pd+HL+3)=PW3
> -- 6D 4B 6D 5B 6D 6B 6D 7B | `LD (`pd`+HL),PX` LD (PW+HL),PX LD (PX+HL),PX LD (PY+HL),PX LD (PZ+HL),PX | 18 (2,2,2,3,3,3,3) | (pd+HL)=PX0; (pd+HL+1)=PX1 (pd+HL+2)=PX2; (pd+HL+3)=PX3
> -- 6D 8B 6D 9B 6D AB 6D BB | `LD (`pd`+HL),PY` LD (PW+HL),PY LD (PX+HL),PY LD (PY+HL),PY LD (PZ+HL),PY | 18 (2,2,2,3,3,3,3) | (pd+HL)=PY0; (pd+HL+1)=PY1 (pd+HL+2)=PY2; (pd+HL+3)=PY3
> -- 6D CB 6D DB 6D EB 6D FB | `LD (`pd`+HL),PZ` LD (PW+HL),PZ LD (PX+HL),PZ LD (PY+HL),PZ LD (PZ+HL),PZ | 18 (2,2,2,3,3,3,3) | (pd+HL)=PZ0; (pd+HL+1)=PZ1 (pd+HL+2)=PZ2; (pd+HL+3)=PZ3

> Flags | ALTD | IOI/IOE
> S | Z | L/V | C | F | R | SP | S | D
> - | - | - | - |  |  |  |  |

> #### Description

> Loads the memory location whose address is computed as the sum of pd and HL with ps (any of the 32-bit registers PW, PX, PY or PZ).

> The address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

> If pd is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).

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