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> LD (pd+HL),rr Load Rabbit 4000 Instruction

> Opcode | Instruction | Clocks | Operation
> `--` 6D 03 6D 13 6D 23 6D 33 | `LD (`pd`+HL),BC` LD (PW+HL),BC LD (PX+HL),BC LD (PY+HL),BC LD (PZ+HL),BC | `12 (2,2,2,3,3)` | `(`pd`+HL)=C;` `(`pd`+HL)=B` (PW+HL)=C; (PW+HL+1)=B (PX+HL)=C; (PX+HL+1)=B (PY+HL)=C; (PY+HL+1)=B (PZ+HL)=C; (PZ+HL+1)=B
> -- 6D 43 6D 53 6D 63 6D 73 | `LD (`pd`+HL),DE` LD (PW+HL),DE LD (PX+HL),DE LD (PY+HL),DE LD (PZ+HL),DE | `12 (2,2,2,3,3)` | `(`pd`+HL)=E;` `(`pd`+HL)=D` (PW+HL)=E; (PW+HL+1)=D (PX+HL)=E; (PX+HL+1)=D (PY+HL)=E; (PY+HL+1)=D (PZ+HL)=E; (PZ+HL+1)=D
> -- 6D 83 6D 93 6D A3 6D B3 | `LD (`pd`+HL),IX` LD (PW+HL),IX LD (PX+HL),IX LD (PY+HL),IX LD (PZ+HL),IX | `12 (2,2,2,3,3)` | `(`pd`+HL)=IX`low`;` `(`pd`+HL)=IX`high (PW+HL)=IXlow;(PW+HL+1)=IXhigh (PX+HL)=IXlow;(PX+HL+1)=IXhigh (PY+HL)=IXlow;(PY+HL+1)=IXhigh (PZ+HL)=IXlow;(PZ+HL+1)=IXhigh
> -- 6D C3 6D D3 6D E3 6D F3 | `LD (`pd`+HL),IY` LD (PW+HL),IY LD (PX+HL),IY LD (PY+HL),IY LD (PZ+HL),IY | `12 (2,2,2,3,3)` | `(`pd`+HL)=IY`low`;` `(`pd`+HL)=IY` high (PW+HL)=IYlow;(PW+HL+1)=IYhigh (PX+HL)=IYlow;(PX+HL+1)=IYhigh (PY+HL)=IYlow;(PY+HL+1)=IYhigh (PZ+HL)=IYlow;(PZ+HL+1)=IYhigh

> Flags | ALTD | IOI/IOE
> S | Z | L/V | C | F | R | SP | S | D
> - | - | - | - |  |  |  |  |

> #### Description

> Loads the memory location whose address is computed as the sum of pd and HL with rr (any of the registers BC, DE, IX or IY). HL is considered sign extended to 24 bits.

> The address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

> If pd is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).

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