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> LD pd,(ps+d) Load Rabbit 4000 Instruction

> Opcode | Instruction | Clocks | Operation
> -- | LD pd,(ps+d) | 15 (2,2,2,1,2,2,2,2) | pd0=(ps+d); pd1=(ps+d+1) pd2=(ps+d+2); pd3=(ps+d+3)
> 6D 08 d | LD PW,(PW+d) | 15 (2,2,2,1,2,2,2,2) | PW0=(ps+d) PW1=(ps+d+1) PW2=(ps+d+2) PW3=(ps+d+3)
> 6D 18 d | LD PW,(PX+d)
> 6D 28 d | LD PW,(PY+d)
> 6D 38 d | LD PW,(PZ+d)
> 6D 48 d | LD PX,(PW+d) | 15 (2,2,2,1,2,2,2,2) | PX0=(ps+d) PX1=(ps+d+1) PX2=(ps+d+2) PX3=(ps+d+3)
> 6D 58 d | LD PX,(PX+d)
> 6D 68 d | LD PX,(PY+d)
> 6D 78 d | LD PX,(PZ+d)
> 6D 88 d | LD PY,(PW+d) | 15 (2,2,2,1,2,2,2,2) | PY0=(ps+d) PY1=(ps+d+1) PY2=(ps+d+2) PY3=(ps+d+3)
> 6D 98 d | LD PY,(PX+d)
> 6D A8 d | LD PY,(PY+d)
> 6D B8 d | LD PY,(PZ+d)
> 6D C8 d | LD PZ,(PW+d) | 15 (2,2,2,1,2,2,2,2) | PZ0=(ps+d) PZ1=(ps+d+1) PZ2=(ps+d+2) PZ3=(ps+d+3)
> 6D D8 d | LD PZ,(PX+d)
> 6D E8 d | LD PZ,(PY+d)
> 6D F8 d | LD PZ,(PZ+d)

> Flags | ALTD | IOI/IOE
> S | Z | L/V | C | F | R | SP | S | D
> - | - | - | - |  | · |  |  |

> #### Description

> Loads pd (any of the 32-bit registers PW, PX, PY or PZ) with the data whose address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

> If ps is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).

> The address is computed as the sum of ps and the 8-bit displacement d.

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