/*
	PLADTG.C
       
   A/D-12 sample program using the Tiny Giant and the special PLCBus
   cable.

   Jumper J2 on the A/D-12 board must be set 1-2 to power the analog
   circuits on the A/D-12 board.
*/

#use "default.h"

#if !((BOARD_TYPE==TINY_GIANT))
#fatal "This program only runs on the Tiny Giant."
#endif

nodebug void PBus4_Addr (int addr, char nyble)
{ 
  char abus, dbus, scr, scr2;
  static char amask[4] = {0x40, 0x50, 0x60, 0x70};

  outport(PIOCB, 0xCF);  /* Mode 3 */ 
  outport(PIOCB, 0x00);  /* all output */  

  --nyble;
  pbus_shadow[nyble] = scr  = (addr >> (nyble << 2)) & 0x0f;  
  dbus = ((scr & 0x05) << 1) | ((scr & 0x0A) >> 1);
  abus = amask[nyble];

  outport(PIODB, (char)(abus | dbus | 1));  /* Simulate cycle by clocking STB */
  outport(PIODB, (char)(abus | dbus | 0));
  outport(PIODB, (char)(abus | dbus | 1));
}

/*** BeginHeader Plad_Rd12 ****************************************/

/* define bit masks for PIO port */
#define BUSAD0 0x40
#define BUSAD1 0x50
#define BUSAD2 0x60
#define BUSWR  0x70
#define BUSRD0 0x00
#define BUSRD1 0x10
#define BUSSPR 0x20
#define BUSRST 0x30
#define STROBE 0x80
#define NSTR   0x7F
#define PLCDTA 0x0F

#define PLCC   PIOCB
#define PLCD   PIODB
#define OUTMSK 0x00
#define ADINMSK   0x02     /* input on ADI for A/DC */
#define EEINMSK   0x01     /* input on SDA for EEPROM */
#define SCKMSK 0xF900   /* DE reg mask for toggling SCLK while getting input */

#define ADSDA  0x01     /* eeprom data line keep high during AD operation */
#define ADSCLK 0x04     /* MGL bit masks for control lines */
#define ADI    0x02
#define ADCS   0x08

#define ADO    0x02

#define BREG   0x0200


   int Plad_Rd12 (int channel);                      /* Fast A/D read */

/*** EndHeader */

/*=========================================================================*\
   int Plad_Rd12(int channel)

   Read A/D on PLC ADC IAB233  12-bit version           12/03/1992

   Reads a 12-bit value from the LT1294 12-bit sample and hold A/D.
   The A/D has 8 input channels.  This function allows reading any
   of these as single-ended inputs or channels 0-1 together as a 
   differential input pair. Also, each can be read as a unipolar or 
   bipolar value.
   

   CHANNEL SELECTION 
   -----------------
   The channel to read, input mode, and polarity are all determined
   by the channel number passed in as a parameter:

      A/D Ch   Polarity    Input                         Gain Stage ?
      ------   --------    -------------------------     ------------
          0:   Bipolar     ANx+ w/respect to A/D gnd          No 
          1:   Bipolar     ANx- w/respect to A/D gnd          No 
        2-7:   Bipolar     ANx+/- differential           Yes (2 to 202)
          8:   Unipolar    ANx+ w/respect to A/D gnd          No 
          9:   Unipolar    ANx- w/respect to A/D gnd          No 
      10-15:   Unipolar    ANx+/- differential           Yes (2 to 202)
         16:   Bipolar     ANx+/- differential                No 
         17:   Unipolar    ANx+/- differential                No 

   * ANx refers to the input mux pair selection AN0 through AN7
   * Channels 2-7, 10-15 have gains of 2,202,22,42,102,6 respectively.

   HARDWARE NOTE
   -------------
   On the analog expansion board, the 8 incoming signal (+/-) pairs 
   are routed through an analog mux pair.  The output of this mux 
   runs through different amplifier stages in parallel which all 
   appear at the input channels of the A/D.  Thus the A/D has 8 
   differenly conditioned inputs of the same signal at it's input 
   at once. The signal gain of each channel is as follows:   

   The first two channels can be used as unity gain single ended 
   inputs or as a unity gain differential pair (they bypass the gain 
   conditioning)

      ch0: Unity Gain of + input signal 
      ch1  Unity Gain of - input signal

   The six other channels are read as single-ended inputs at the A/D
   with a specified gain (although they come into the board as a 
   differential pair:

      ch2   Gain=2   of (+/-) input pair
      ch3   Gain=202 of (+/-) input pair
      ch4   Gain=22  of (+/-) input pair
      ch5   Gain=42  of (+/-) input pair
      ch6   Gain=102 of (+/-) input pair
      ch7   Gain=6   of (+/-) input pair


   RETURN VALUE
   ------------
   The output of the function is a 12-bit number representing a voltage
   depending on the polarity chosen:

     Bipolar mode:  -2048 to +2047  representing -2.5v to +2.5v
     Unipolar mode:     0 to  4095  representing    0v to +2.5v
     Error reported:        0x8000  error reading A/D


   SETUP
   -----
   To use this function, the PLCBus address must have been set up to
   address this board and PAL register S3B must be enabled.  See manual
   for details.  Also the analog mux must be set up to route the 
   proper input signal to the A/D


   EXECUTION TIME
   -------------
   Execution time for this function is appx. 560 us.  

   Switching of the analog mux requires some delay time for the input
   to settle within 1 lsb.  The amount of settle time necessary depends
   on the gain to be read: 400us @ G202, 200us @ G102, 90us @ G42, 63us @
   G22, 10us @ G6 , 7us @ G2, and 1us @ G1. 


   DROOP DUE TO INTERRUPTS
   -----------------------
   The A/D performs a sample-and-hold of the input signal.  Interrupts
   can reduce the accuracy of the A/D due to droop of the held input
   while servicing occurs. The LTC 1294 will droop 1/10 lsb after 160us.
   If possible, disable interrupts while calling this function.

   This function takes 560 microseconds to execute on standard TG.
   
\*=========================================================================*/
#asm nodebug
;       **** A/D Control word table for each channel 0-17 ****
adtbl:  db  0C3h,0C7h,0D3h,0D7h,0CBh,0CFh,0DBh,0DFh     ; single mode -bipolar
        db  0E3h,0E7h,0F3h,0F7h,0EBh,0EFh,0FBh,0FFh     ; sm - uni 
        db  0C1h,0E1h                                   ; diff mode uni, bi


Plad_Rd12::
         ld    de,adtbl       ; de=table addr 
         add   hl,de          ;                                      
         ld    a,(hl)         ; get control word
         push  af             ; save code

         ld    l,a            
         
         ld    bc, PLCC        ; set PIOA to output
         ld    a, 0xCF
         out   (c), a
         ld    a, OUTMSK
         out   (c), a
         
         ld    bc, PLCD
         ld    d, STROBE
         ld    e, NSTR
nullclk:
         ld    a, BUSWR      ; /ADCS=0 SCLK=0 ADI=0 SDA=1 
         or    ADSDA
         or    d        
         out   (c),a         ; /ADCS high
         and   e   
         out   (c),a         ; Clock in 
         or    d
         out   (c),a         

         or    ADCS          ; /ADCS=1 SCLK=0 ADI=0 SDA=1
         out   (c),a         ; 
         and   e
         out   (c),a         ; Clock in 
         or    d
         out   (c),a         ;

         or    ADSCLK        ; /ADCS=1 SCLK=1 ADI=0 SDA=1
         out   (c),a         ; /ADCS low
         and   e
         out   (c),a         ; Clock in 
         or    d
         out   (c),a         ;

         ld    a, BUSWR         ;for clearing ADI in accumulator
         or    STROBE
         or    ADSDA
         or    ADCS
         ld    d, a
         
         ld    e, 0            ;for ADC
         ld    h, ADI         ; for ADI set bit
  
; Send Control word to A/D 
         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad0        ;
         or    h              ; set ADI
ad0:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad1        ;
         or    h              ; set ADI
ad1:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad2        ;
         or    h              ; set ADI
ad2:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad3        ;
         or    h              ; set ADI
ad3: 
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad4        ;
         or    h              ; set ADI
ad4:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

; Sample and hold happens after input channel is selected
; disable interrupts now to avoid errors due to droop
; droop is 1/10 lsb after 160 us

#ifndef NODISINT
         ex  af,af'
         ld  a,i     ;save interrupt state
         ex  af,af'
         di              ;disable interrupts
#endif

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad5        ;
         or    h              ; set ADI
ad5:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad6        ;
         or    h              ; set ADI
ad6:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         and   d              ;for ADI bit clear
         rr    l              ;shift right first bit to carry
         jr    nc, ad7        ;
         or    h              ; set ADI
ad7:         
         out   (c),a          ;/ADCS SCLK low ADI=control bit
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

         or    ADSCLK          ;SCLK high
         out   (c),a         ;
         and   NSTR
         out   (c),a         ; Clock in 
         or    STROBE
         out   (c),a         ;

; Read in the serial data now on ADI (analog serial data output).
; Each bit is read in to the a-register MSB, and pushed onto the stack,
; Shifting is delayed until all of the bits are read in.
; LTC1294 serial clock freq: 1Mhz - .1Mhz range allowed.
;

         ld    bc, PLCC
         ld    a, 0xCF
         out   (c), a           ; reset mode to input on ADO
         ld    a, ADINMSK
         out   (c), a     ;

         ld    h, STROBE      ;
         ld    l, NSTR
         
         ld    bc, PLCD       ;bc = PLCBus write address
         ld    de, SCKMSK     ;d=mask for hi-clock:  /ADCS=1 SCLK=0 ADI=0 SDA=1

         ld    a, d
         out   (c),a          ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c),a          ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

; get bit 0 
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later
         
; get bit 1
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 2
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 3
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 4
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 5
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 6
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 7
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 8
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 9
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 10
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

; get bit 11
         ld    a, d
         out   (c), a         ;SCLK low, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a
         
         or    ADSCLK
         out   (c), a         ;SCLK high, /ADCS low, SDA high, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

         out   (c), h         ; read from PLC Bus  STROBE only
         out   (c), e         ; STROBE low
         in    a, (c)         ;read in ADI to bit 0
         out   (c), h
         push  af             ; store input for assembling return later

         ld    bc, PLCC       ; reset PIO to all output
         ld    a, 0xCF
         out   (c), a           ; reset mode to input on ADO
         ld    a, OUTMSK
         out   (c), a     ;
         
         ld    bc, PLCD
         ld    a, BUSWR       ; Shut down A/DC
         or    STROBE
         out   (c), a         ;SCLK low, /ADCS high, SDA low, ADI low
         and   l
         out   (c), a
         or    h
         out   (c), a

; make return value by popping accumulator off of stack and shifting ADI into hl

         ld    hl, 0000
         ld    b, 8           ; shift into l only
hlloop1:
         pop   af             ; get next
         and   ADO            ; test for bit, while clearing carry
         jr    z, notc1
         scf                  ; set bit for shift
notc1:
         rr    h              ; shift into h
         djnz  hlloop1
         
         ld    b, 4
hlloop2:
         pop   af             ; get next
         and   ADO            ; test for bit, while clearing carry
         jr    z, notc2
         scf                  ; set bit for shift
notc2:
         rr    h              ; shift into l
         rr    l              ; shift overflow into h
         djnz  hlloop2

         rr    h              ; finish shifting right 
         rr    l
         rr    h
         rr    l
         rr    h
         rr    l
         rr    h
         rr    l

; restore interrupts if disabled
#ifndef NODISINT
         ex  af,af'
         jp  po,skipei        ;if interrupts were off
         ei
#endif
skipei:

; hl now has 12 bit value - Do sign extension for bipolar mode
signex:
         pop     af              ; Restore Flags                        
         and     20h             ; Check if bipolor operation           
         jr      nz,donead       ; Skip Sign extension                  
         bit     3,h             ; Check if Sign Extension Required     
         jr      z,donead        ; Skip Sign extension                  
         ld      a,0F0h          ; Do sign extension
         or      h               ;
         ld      h,a             ;
                                 ;
donead:
                                 ;
         ret                     ;
#endasm                                                              

/*** BeginHeader AN_Input_Ch */

   int AN_Input_Ch (int bd_addr, int channel);       /* Set Analog Mux */

/*** EndHeader */

/************************************************************************ 
AN_Input_Ch   - selects the input pair AN+/AN- from the two input muxes 
                on the currently selected analog board.

 INPUT MUX CONTROL TABLE 
   Only one MUX(U11 or U12) can be turned on at a time.  They are controlled
   by the A-register (U13-74HC174) on the A/D board.  
                                
           Control bits off A-Register                                         
  an(+/-)     ON2   ON1   AC1   AC0    Wr. to A-reg to sel.
    0          0     1     0     0            0x04        
    1          0     1     0     1            0x05        
    2          0     1     1     0            0x06        
    3          0     1     1     1            0x07        
    4          1     0     0     0            0x08        
    5          1     0     0     1            0x09        
    6          1     0     1     0            0x0a        
    7          1     0     1     1            0x0b        
************************************************************************/

nodebug AN_Input_Ch (int bd_addr, int channel)
{ 
   PBus12_Addr (bd_addr);         /* set address to analog board, A-Register */ 
   PBus4_Write ((char) (channel + 4));     /* S3A=1: ON2 ON1 AC1 AC0   */
   PBus4_Addr ((bd_addr | BREG), 3);    /* Set back to b-reg, for A/D reading*/
}  

/*** BeginHeader  Plcad_Addr */

   int Plcad_Addr(int bdnum);                       /* Calc. board address */

/*** EndHeader */

/*************************************************************************
  Plcad_Addr 
  
  Converts logical board address 0-63 to 12-bit (3-nybble) PLCBus
  analog address. Returns integer value in hl.

   address format: 000p 10pj pp0j
             pppp: 4-bit Pal identifier from number: 46P0 P=pppp
               jj: analog board jumpers bd0, bd1 (address 0-3)

   equivalent C function:
     int plcad_addr(int bdnum)
     { return ((bdnum&0x22)<<3) + ((bdnum&0x10)<<1) +  (bdnum&0x0d) + 0x80;}
     
   execution time:
      Clock Cycles:    Max: 97        Min: 87 
      Time @ 9.216Mhz: Max: 10.5us    Min: 9.41us
*************************************************************************/

#asm nodebug
Plcad_Addr::                                                     ;cycle count
     ld  a,l         ;construct mid & lo nybbles in a                   4
     ld  h,0h        ;h contains high nybble - 0000 or 0001             6
hinybl:
     bit 5,a        ;Hi-nybble = 0000 for boards 0-31, 0001 for 32-63   6
     jr  z,lonybl                                                      ;6-8
     inc h                                                             ;4
lonybl:
     and 0dh        ;low nybble same, except d1=0                       6
midnybl:
     bit 1,l        ;bit 0 of mid nybble = bit 1 of board addr          6
     jr  z,bit1                                                        ;6-8
     or  10h                                                           ;6
bit1:
     bit 4,l        ;bit 1 of mid nybble = bit 4 of board addr          6
     jr  z,bit3                                                        ;6-8
     or  20h                                                           ;6
bit3:
     or  80h        ;bit3=1                                             6
     ld  l,a        ;move back to l reg, hl = physical address          4

     ;Switch nybbles around
     ld  a,h  
     and 0fh
     ld  c,a    ;c = 0 , hi-nybble

     ld  a,l
     and 0fh
     ld  h,a    ;h=0 , lo nybb

     ld  a,l    ;a = mid, lo
     and 0f0h   ;a = mid , 0
     or  c      ;a = mid, hi 
     ld  l,a    ;l = mid, hi
     ret                                                               
#endasm

/*************************************** end of EXP-AD12 drivers for TG **/


int bd_addr;
int j, chan, an;

main ()
{
   bd_addr = Plcad_Addr (3);              /* Make board address */
   an = chan = 0;
   
   while (1)
   {
      AN_Input_Ch (bd_addr, an);          /* switch to new input channel */
      for (j = 0; j < 15000; ++j) hitwd(); /* let the new channel settle */
   
      printf ("Input AN %d = %x\n", an, Plad_Rd12 (chan));
      runwatch ();
      if (++an > 7)
         an = 0;
   }
 }

/***************************************** end of PLADTG.C *********/
