RabbitCore RCM3000 User's Manual

> ## Appendix F. Motor Control Option

> The RCM3000/RCM3100 Prototyping Board has a header at J6 for a motor control option. While Z-World and Rabbit Semiconductor do not support this option at this time, this appendix provides additional information about Parallel Port F on the Rabbit 3000 microprocessor to enable you to use this feature on the Prototyping Board for your needs.

> ### F.1 Overview

> The Parallel Port F connector on the Prototyping Board, J6, gives access to all 8 pins of Parallel Port F, along with +5 V. This appendix describes the function of each pin, and the ways they may be used for motion-control applications. It should be read in conjunction with the Rabbit 3000 Microprocessor User's Manual and the RCM3000 and the RCM3000/RCM3100 Prototyping Board schematics.

> ### F.2 Header J6

> The connector is a 2 × 5, 0.1" pitch header suitable for connecting to a IDC receptacle, with the following pin allocations.

> Table F-1. RCM3000/RCM3100 Prototyping Board Header J6 Pinout
> Pin | Rabbit 3000 | Primary Function | Alternate Function 1 | Alternate Function 2
> 1 | Parallel Port F, bit 0 | General-purpose I/O port | Quadrature decoder 1 Q input | SCLK_D
> 2 | Parallel Port F, bit 1 | General-purpose I/O port | Quadrature decoder 1 I input | SCLK_C
> 3 | Parallel Port F, bit 2 | General-purpose I/O port | Quadrature decoder 2 Q input | -
> 4 | Parallel Port F, bit 3 | General-purpose I/O port | Quadrature decoder 2 I input | -
> 5 | Parallel Port F, bit 4 | General-purpose I/O port | PWM[0] output | Quadrature decoder 1 Q input
> 6 | Parallel Port F, bit 5 | General-purpose I/O port | PWM[1] output | Quadrature decoder 1 I input
> 7 | Parallel Port F, bit 6 | General-purpose I/O port | PWM[2] output | Quadrature decoder 2 Q input
> 8 | Parallel Port F, bit 7 | General-purpose I/O port | PWM[3] output | Quadrature decoder 2 I input
> 9 | +5 V | External buffer logic supply
> 10 | 0 V | Common

> All Parallel Port F lines (pins 1 to 8) are pulled up internally to +3.3 V via 100 kW resistors. When used as outputs, the port pins will sink up to 6 mA at a VOL of 0.4 V max. (0.2 V typ), and source up to 6 mA at a VOH of 2.2 V typ. When used as inputs, all pins are 5 V tolerant.

> As the outputs from Parallel Port F are compatible with 3.3 V logic, buffers may be needed when the external circuit drive requirements exceed the 2.2 V typ logic high and/or the 6 mA maximum from the Rabbit 3000. The +5 V supply output is provided for supplying interface logic. When used as inputs, the pins on header J6 do not require buffers unless the input voltage will exceed the 5 V tolerance of the processor pins. Usually, a simple resistive divider with catching diodes will suffice if higher voltage inputs are required. If the outputs are configured for open-drain operation, they may be pulled up to +5 V (while observing the maximum current, of course).

> ### F.3 Using Parallel Port F

> Parallel Port F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register. As outputs, the bits of the port are buffered, with the data written to the Port F Data Register transferred to the output pins on a selected timing edge. The outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing. These inputs and outputs are also used for access to other peripherals on the chip.

> As outputs, Parallel Port F can carry the four Pulse Width Modulator outputs on PF4-PF 7 (J6, pins 5-8). As inputs, Parallel Port F can carry the inputs to the Quadrature Decoders on PF0-PF3 (J6, pins 1-4). When Serial Port C or Serial Port D is used in clocked serial mode, two pins of Port F (PF0 / J6:1 and PF1 / J6:2) are used to carry the serial clock signals. When the internal clock is selected in these serial ports, the corresponding bit of Parallel Port F is set as an output.

> #### F.3.1 Parallel Port F Registers

> Data Direction Register--PFDDR, address 00111111 (0x3F), write-only, default value on reset 00000000. For each bit position, write a 1 to make the corresponding port line an output, or 0 to produce an input.

> Drive Control Register--`PFDCR`, address 00111110 (0x3E), Write-only, no default on reset (port defaults to all inputs). Effective only if the corresponding port bits are set as outputs, each bit set to 1 configures the corresponding port bit as open drain. Setting the bit to 0 configures that output as active high or low.

> Function Register--`PFFR`, address 00111101 (0x3D), Write-only, no default on reset. This register sets the alternate output function assigned to each of the pins of the port. When set to 0, the corresponding port pin functions normally as an output (if configured to be an output in `PFDDR`). When set to 1, each bit sets the corresponding pin to have the alternate output function as shown in the summary table at the end of this section.

> Control Register--`PFCR`, address 00111100 (0x3C), Write-only, default on reset xx00xx00. This register sets the transfer clock, which controls the timing of the outputs on each nibble of the output ports to allow close synchronization with other events. The summary table at the end of this section shows the settings for this register. The default values on reset transfer the output values on `CLK`/2.

> Data Register--`PFDR`, address 00111000 (0x38), Read or Write, no default value on reset. On read, the current state of the pins is reported. On write, the output buffer is written with the value for transfer to the output port register on the next rising edge of the transfer clock, set in the `PFCR`.

> Table F-2. Parallel Port F Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset Value
> Port F Data Register | PFDR | 00111000 (0x38) | R/W | xxxxxxxx
> Bits | Value | Description
> 0:7 | Read | Current state of pins
> | Write | Port buffer. Value transferred to O/P register on next rising edge of transfer clock.
> Port F Control Register | PFCR | 00111100 (0x3C) | W only | xx00xx00
> Bits | Value | Description
> 0:1 | 00 | Lower nibble transfer clock is CLK/2
> | 01 | Lower nibble transfer clock is Timer A1
> | 10 | Lower nibble transfer clock is Timer B1
> | 11 | Lower nibble transfer clock is Timer B2
> 2:3 | xx | These bits are ignored
> 4:5 | 00 | Upper nibble transfer clock is CLK/2
> | 01 | Upper nibble transfer clock is Timer A1
> | 10 | Upper nibble transfer clock is Timer B1
> | 11 | Upper nibble transfer clock is Timer B2
> 6:7 | xx | These bits are ignored
> Port F Function Register | PFFR | 00111101 (0x3D) | W | xxxxxxxx
> Bits | Value | Description
> 0:7 | 0 | Corresponding port bits function normally
> 0 | 1 | Bit 0 carries SCLK_D
> 1 | 1 | Bit 1 carries SCLK_C
> 2:3 | x | No effect
> 4 | 1 | Bit 4 carries PWM[0] output
> 5 | 1 | Bit 5 carries PWM[1] output
> 6 | 1 | Bit 6 carries PWM[2] output
> 7 | 1 | Bit 7 carries PWM[3] output
> Port F Drive Control Register | PFDCR | 00111110 (0x3E) | W | xxxxxxxx
> Bits | Value | Description
> 0:7 | 0 | Corresponding port bit is active high or low
> | 1 | Corresponding port bit is open drain
> Port F Data Direction Register | PFDDR | 00111111 (0x3F) | W | 00000000
> Bits | Value | Description
> 0:7 | 0 | Corresponding port bit is an input
> | 1 | Corresponding port bit is an output

> ### F.4 PWM Outputs

> The Pulse-Width Modulator consists of a 10-bit free-running counter and four width registers. Each PWM output is high for n + 1 counts out of the 1024-clock count cycle, where n is the value held in the width register. The PWM output high time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output. The PWM is clocked by the output of Timer A9. The spreading function is implemented by dividing each 1024-clock cycle into four quadrants of 256 clocks each. Within each quadrant, the Pulse-Width Modulator uses the eight MSBs of each pulse-width register to select the base width in each of the quadrants. This is the equivalent to dividing the contents of the pulse-width register by four and using this value in each quadrant. To get the exact high time, the Pulse-Width Modulator uses the two LSBs of the pulse-width register to modify the high time in each quadrant according to Table F-3 below. The "n/4" term is the base count, and is formed from the eight MSBs of the pulse-width register.

> Table F-3. PWM Outputs
> Pulse Width LSBs | 1st | 2nd | 3rd | 4th
> 00 | n/4 + 1 | n/4 | n/4 | n/4
> 01 | n/4 + 1 | n/4 | n/4 + 1 | n/4
> 10 | n/4 + 1 | n/4 + 1 | n/4 + 1 | n/4
> 11 | n/4 + 1 | n/4 + 1 | n/4 + 1 | n/4 + 1

> The diagram below shows a PWM output for several different width values for both modes of operation. Operation in the spread mode reduces the filtering requirements on the PWM output in most cases.

> Figure F-1. PWM Outputs for Various Normal and Spread Modes

> ### F.5 PWM Registers

> There are no default values on reset for any of the PWM registers.

> Table F-4. PWM Registers
> PWM LSBs | Register | Address
> | PWL0R | 10001000 (0x88)
> | PWL1R | 10001010 (0x8A)
> | PWL2R | 10001100 (0x8C)
> | PWL3R | 10001110 (0x8E)
> Bit(s) | Value | Description
> 7:6 | Write | The least significant two bits for the Pulse Width Modulator count are stored
> 5:1 |  | These bits are ignored.
> 0 | 0 | PWM output High for single block.
> | 1 | Spread PWM output throughout the cycle
> PWM MSB x | Register | Address
> | PWM0R | Address = 10001001 (0x89)
> | PWM1R | Address = 10001011 (0x8B)
> | PWM2R | Address = 10001101 (0x8D)
> | PWM3R | Address = 10001111 (0x8F)
> Bit(s) | Value | Description
> 7:0 | write | The most significant eight bits for the Pulse-Width Modulator count are stored With a count of n, the PWM output will be high for n +1 clocks out of the 1024 clocks of the PWM counter.

> ### F.6 Quadrature Decoder

> The two-channel Quadrature Decoder accepts inputs via Parallel Port F from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an in-phase (I) and a quadrature-phase (Q) signal, and provides 8-bit counters to track shaft rotation and provide interrupts when the count goes through the zero count in either direction. The Quadrature Decoder contains digital filters on the inputs to prevent false counts and is clocked by the output of Timer A10. Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Parallel Port F. The I signal is input on an odd-numbered port bit, while the Q signal is input on an even-numbered port bit. There is also a disable selection, which is guaranteed not to generate a count increment or decrement on either entering or exiting the disable state. The operation of the counter as a function of the I and Q inputs is shown below.

> Figure F-2. Operation of Quadrature Decoder Counter

> The Quadrature Decoders are clocked by the output of Timer A10, giving a maximum clock rate of one-half of the peripheral clock rate. The time constant of Timer A10 must be fast enough to sample the inputs properly. Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock periods wide. In addition, the clock rate must be high enough that transitions on the I and Q inputs are sampled in different clock cycles. The Input Capture (see the Rabbit 3000 Microprocessor Users Manual) may be used to measure the pulse width on the I inputs because they come from the odd-numbered port bits. The operation of the digital filter is shown below.

> The Quadrature Decoder generates an interrupt when the counter increments from 0x00 to 0x01 or when the counter decrements from 0x00 to 0xFF. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDCSR.

> Table F-5. Quadrature Decoder Registers
> Register Name | Mnemonic | Address
> Quad Decode Control/Status Register | QDCSR | 10010000 (0x90)
> Bit | Value | Description
> 7 (rd-only) | 0 | Quadrature Decoder 2 did not increment from 0xFF.
> | 1 | Quadrature Decoder 2 incremented from 0xFF to 0x00. This bit is cleared by a read of this register.
> 6 (rd-only) | 0 | Quadrature Decoder 2 did not decrement from 0x00.
> | 1 | Quadrature Decoder 2 decremented from 0x00 to 0xFF. This bit is cleared by a read of this register
> 5 | 0 | This bit always reads as zero.
> 4 (wr-only) | 0 | No effect on the Quadrature Decoder 2.
> | 1 | Reset Quadrature Decoder 2 to 0x00, without causing an interrupt.
> 3 (rd-only) | 0 | Quadrature Decoder 1 did not increment from 0xFF.
> | 1 | Quadrature Decoder 1 incremented from 0xFF to 0x00. This bit is cleared by a read of this register.
> 2 (rd-only) | 0 | Quadrature Decoder 1 did not decrement from 0x00.
> | 1 | Quadrature Decoder 1 decremented from 0x00 to 0xFF. This bit is cleared by a read of this register.
> 1 | 0 | This bit always reads as zero.
> Bit | Value | Description
> 0 (wr-only) | 0 | No effect on the Quadrature Decoder 1.
> | 1 | Reset Quadrature Decoder 1 to 0x00, without causing an interrupt.
> Quad Decode Control Register | QDCR | Address = 10010001 (0x91)
> Bit | Value | Description
> 7:6 | 0x | Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement.
> | 10 | Quadrature Decoder 2 inputs from Port F bits 3 and 2.
> | 11 | Quadrature Decoder 2 inputs from Port F bits 7 and 6.
> 5:4 | xx | These bits are ignored.
> 3:2 | 0x | Disable Quadrature Decoder 1 inputs. Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement.
> | 10 | Quadrature Decoder 1 inputs from Port F bits 1 and 0.
> | 11 | Quadrature Decoder 1 inputs from Port F bits 5 and 4.
> 1:0 | 0 | Quadrature Decoder interrupts are disabled.
> | 1 | Quadrature Decoder interrupt use Interrupt Priority 1.
> | 10 | Quadrature Decoder interrupt use Interrupt Priority 2.
> | 11 | Quadrature Decoder interrupt use Interrupt Priority 3.
> Quad Decode Count Register | QDC1R | Address = 10010100 (0x94)
> | (QDC2R) | Address = 10010110 (0x96)
> Bit(s) | Value | Description
> 7:0 | read | The current value of the Quadrature Decoder counter is reported.

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