Rabbit 3000 Microprocessor User's Manual

> ## 12. Rabbit Serial Ports

> The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can perform asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC synchronous communications in addition to standard asynchronous communications. Port A has the special capability of being used to remote boot the microprocessor via asynchronous, synchronous, or IrDA (asynchronous serial).

> Table 12-1 lists the synchronous serial port signals.

> Table 12-1. Serial Port Signals
> Serial Port | Signal Name | Function
> Serial Port A | TXA | Serial Transmit Out
> | RXA | Serial Transmit In
> | CLKA | Clock for clocked mode (bidirectional)
> | ATXA | Alternate serial transmit out
> | ARXA | Alternate serial receive in
> Serial Port B | TXB | Serial Transmit Out
> | RXB | Serial Transmit In
> | CLKB | Clock for clocked mode (bidirectional)
> | ATXB | Alternate serial transmit out
> | ARXB | Alternate serial receive in
> Serial Port C | TXC | Serial Transmit Out
> | RXC | Serial Transmit In
> | CLKC | Clock for clocked mode (bidirectional)
> Serial Port D | TXD | Serial Transmit Out
> | RXD | Serial Transmit In
> | CLKD | Clock for clocked mode (bidirectional)
> Serial Port E | TXE | Serial Transmit Out
> | RXE | Serial Transmit In
> | TCLKE | Optional external transmit clock
> | RCLKE | Optional external receive clock
> Serial Port F | TXF | Serial Transmit Out
> | RXF | Serial Transmit In
> | TCLKF | Optional external transmit clock
> | RCLKF | Optional external receive clock

> Figure 12-1 shows a block diagram of the serial ports.

> Figure 12-1. Block Diagram of Rabbit Serial Ports

> The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th" bit or address bit mode of operation is also supported. The "9th" bit can be set high or low by accessing the appropriate serial port register. Although Parity and multiple stop bits are not directly supported by the hardware, the "9th" bit can be used to issue an extra stop bit (9th-bit high) or toggled to indicate parity.

> ### 12.1 Serial Port Register Layout

> Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmission. The least significant bit (LSB) is always transmitted first. This is true for both asycnchronous and synchronous communication. If the write is performed to an alternate data register address, the extra address bit or 9th bit (8th bit if 7 data bits) is sent. When data bits have been received, they are read from the data register (LSB first). The control register is used to set the transmit and receive parameters. The status register may be tested to check on the operation of the serial port.

> Figure 12-2. Functional Block Diagram of a Serial Port

> The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. Timers A2-A7 supply the input clock for Serial Ports A-F. These timers can divide the frequency by any number from 1 to 256 (see Chapter 11). The input frequency to the timers can be selected in different ways described in the documentation for the timers. One choice is the peripheral clock--with that choice and a well-chosen crystal frequency for the main oscillator, the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer A0 at the highest Rabbit clock frequencies (see Section A.4 in Appendix A).

> ### 12.2 Serial Port Registers

> Each serial port has 6 registers shown in the tables below. The status, control and extended registers may have somewhat different formats for different serial ports.

> Table 12-2. Serial Port A Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port A Data Register | SADR | 0xC0 | R/W | xxxxxxxx
> Serial Port A Address Register | SAAR | 0xC1 | W | xxxxxxxx
> Serial Port A Long Stop Register | SALR | 0xC2 | W | xxxxxxxx
> Serial Port A Status Register | SASR | 0xC3 | R | 0xx00000
> Serial Port A Control Register | SACR | 0xC4 | W | xx000000
> Serial Port A Extended Register | SAER | 0xC5 | W | 00000000

> Table 12-3. Serial Port B Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port B Data Register | SBDR | 0xD0 | R/W | xxxxxxxx
> Serial Port B Address Register | SBAR | 0xD1 | W | xxxxxxxx
> Serial Port B Long Stop Register | SBLR | 0xD2 | W | xxxxxxxx
> Serial Port B Status Register | SBSR | 0xD3 | R | 0xx00000
> Serial Port B Control Register | SBCR | 0xD4 | W | xx000000
> Serial Port B Extended Register | SBER | 0xD5 | W | 00000000

> Table 12-4. Serial Port C Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port C Data Register | SCDR | 0xE0 | R/W | xxxxxxxx
> Serial Port C Address Register | SCAR | 0xE1 | W | xxxxxxxx
> Serial Port C Long Stop Register | SCLR | 0xE2 | W | xxxxxxxx
> Serial Port C Status Register | SCSR | 0xE3 | R | 0xx00000
> Serial Port C Control Register | SCCR | 0xE4 | W | xx000000
> Serial Port C Extended Register | SCER | 0xE5 | W | 00000000

> Table 12-5. Serial Port D Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port D Data Register | SDDR | 0xF0 | R/W | xxxxxxxx
> Serial Port D Address Register | SDAR | 0xF1 | W | xxxxxxxx
> Serial Port D Long Stop Register | SDLR | 0xF2 | W | xxxxxxxx
> Serial Port D Status Register | SDSR | 0xF3 | R | 0xx00000
> Serial Port D Control Register | SDCR | 0xF4 | W | xx000000
> Serial Port D Extended Register | SDER | 0xF5 | W | 00000000

> Table 12-6. Serial Port E Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port E Data Register | SEDR | 0xC8 | R/W | xxxxxxxx
> Serial Port E Address Register | SEAR | 0xC9 | W | xxxxxxxx
> Serial Port E Long Stop Register | SELR | 0xCA | W | xxxxxxxx
> Serial Port E Status Register | SESR | 0xCB | R | 0xx00000
> Serial Port E Control Register | SECR | 0xCC | W | xx000000
> Serial Port E Extended Register | SEER | 0xCD | W | 000x000x

> Table 12-7. Serial Port F Registers
> Register Name | Mnemonic | I/O Address | R/W | Reset
> Serial Port F Data Register | SFDR | 0xD8 | R/W | xxxxxxxx
> Serial Port F Address Register | SFAR | 0xD9 | W | xxxxxxxx
> Serial Port F Long Stop Register | SFLR | 0xDA | W | xxxxxxxx
> Serial Port F Status Register | SFSR | 0xDB | R | 0xx00000
> Serial Port F Control Register | SFCR | 0xDC | W | xx000000
> Serial Port F Extended Register | SFER | 0xDD | W | 000x000x

> Table 12-8. Data Register All Ports
> Serial Port x Data Register (SADR) (Address = 0xC0) (SBDR) (Address = 0xD0) (SCDR) (Address = 0xE0) (SDDR) (Address = 0xF0) (SEDR) (Address = 0xC8) (SFDR) (Address = 0xD8)
> Bit(s) | Value | Description
> 7:0 | Read | Returns the contents of the receive buffer.
> Write | Loads the transmit buffer with a data byte for transmission.

> Table 12-9. Address Register All Ports
> Serial Port x Address Register (SAAR) (Address = 0xC1) (SBAR) (Address = 0xD1) (SCAR) (Address = 0xE1) (SDAR) (Address = 0xF1) (SEAR) (Address = 0xC9) (SFAR) (Address = 0xD9)
> Bit(s) | Value | Description
> 7:0 | Read | Returns the contents of the receive buffer. In Clocked Serial mode reading the data from this register automatically causes the receiver to start a byte receive operation (the current contents of the receive buffer are read first), eliminating the need for software to issue the Start Receive command.
> Write | Loads the transmit buffer with an address byte, marked with a "zero" address bit, for transmission. In HDLC mode, the last byte of a frame must be written to this register to enable subsequent CRC and closing Flag transmission. In Clocked Serial mode writing the data to this register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command.

> Table 12-10. Long Stop Register All Ports
> Serial Port x Long Stop Register (SALR) (Address = 0xC2) (SBLR) (Address = 0xD2) (SCLR) (Address = 0xE2) (SDLR) (Address = 0xF2) (SELR) (Address = 0xCA) (SFLR) (Address = 0xDA)
> Bit(s) | Value | Description
> 7:0 | Read | Returns the contents of the receive buffer.
> Write | Loads the transmit buffer with an address byte, marked with a "one" address bit, for transmission. In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission.

> Table 12-11. Status Register Asynchronous Mode Only (All Ports)
> Serial Port x Status Register (SASR) (Address = 0xC3) (SBSR) (Address = 0xD3) (SCSR) (Address = 0xE3) (SDSR) (Address = 0xF3) (SESR) (Address = 0xCB) (SFSR) (Address = 0xDB)
> Bit(s) | Value | Description (Async mode only)
> 7 | 0 | The receive data register is empty--no input character is ready.
> 1 | There is a byte in the receive buffer. The transition from "0" to "1" sets the receiver interrupt request flip-flop. The interrupt FF is cleared when the character is read from the data buffer. The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer.
> 6 | 0 | The byte in the receive buffer is data, received with a valid Stop bit.
> 1 | Address bit or 9th (8th) bit received. This bit is set if the character in the receiver data register has a 9th (8th) bit. This bit is cleared and should be checked before reading a data register since a new data value with a new address bit may be loaded immediately when the data register is read. The byte in the receive buffer is an address, or a byte with a framing error. If an address bit is not expected. If the data in the buffer is all zeros, this may be a Break.
> 5 | 0 | The receive buffer was not overrun.
> 1 | This bit is set if the receiver is overrun. This happens if the shift register and the data register are full and a start bit is detected. This bit is cleared when the receiver data register is read.
> 4 | 0 | This bit is always zero in async mode.
> 3 | 0 | The transmit buffer is empty.
> 1 | Transmitter data buffer full. This bit is set when the transmit data register is full, that is, a byte is written to the serial port data register. It is cleared when a byte is transferred to the transmitter shift register or FIFO, or a write operation is performed to the serial port status register. This bit will request an interrupt on the transition from 1 to 0 if interrupts are enabled. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register.
> 2 | 0 | The transmitter is idle.
> 1 | Transmitter busy bit. This bit is set if the transmitter shift register is busy sending data. It is set on the falling edge of the start bit, which is also the clock edge that transfers data from the transmitter data register to the transmitter shift register. The transmitter busy bit is cleared at the end of the stop bit of the character sent. This bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent (there are no more data in the transmitter data register).
> 1:0 | 00 | These bits are always zero in async mode.

> Table 12-12. Status Register Clocked Serial (Ports A-D only)
> Serial Port x Status Register (SASR) (Address = 0xC3) (SBSR) (Address = 0xD3) (SCSR) (Address = 0xE3) (SDSR) (Address = 0xF3)
> Bit(s) | Value | Description (Clocked serial mode only)
> 7 | 0 | The receive data register is empty
> 1 | There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty.
> 6 | 0 | This bit is always zero in clocked serial mode.
> 5 | 0 | The receive buffer was not overrun.
> 1 | The receive buffer was overrun. This bit is cleared by reading the receive buffer.
> 4 | 0 | This bit is always zero in clocked serial mode.
> 3 | 0 | The transmit buffer is empty.
> 1 | The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register.
> 2 | 0 | The transmitter is idle.
> 1 | The transmitter is sending a byte. An interrupt is generated when the transmitter clears this bit, which occurs only if the transmitter is ready to start sending another byte but the transmit buffer is empty.
> 1:0 | 00 | These bits are always zero in clocked serial mode.

> Table 12-13. Status Register HDLC Mode (Ports E and F only)
> Serial Port x Status Register (SESR) (Address = 0xCB) (SFSR) (Address = 0xD3)
> Bit(s) | Value | Description (HDLC mode only)
> 7 | 0 | The receive data register is empty
> 1 | There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty.
> 6,4 | 00 | The byte in the receive buffer is data.
> 01 | The byte in the receive buffer was followed by an Abort.
> 10 | The byte in the receive buffer is the last in the frame, with valid CRC.
> 11 | The byte in the receive buffer is the last in the frame, with a CRC error.
> 5 | 0 | The receive buffer was not overrun.
> 1 | The receive buffer was overrun. This bit is cleared by reading the receive buffer.
> 3 | 0 | The transmit buffer is empty.
> 1 | The transmit buffer is not empty. The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer, unless the byte is marked as the last in the frame. Transmit interrupts are cleared when the transmit buffer is written, or any value (which will be ignored) is written to this register.
> 2:1 | 00 | Transmit interrupt due to buffer empty condition.
> 01 | Transmitter finished sending CRC. An interrupt is generated at the end of CRC transmission. Data written in response to this interrupt will cause only one Flag to be transmitted between frames, and no interrupt will be generated by this Flag.
> 10 | Transmitter finished sending an Abort. An interrupt is generated at the end of an Abort transmission.
> 11 | The transmitter finished sending a closing Flag. Data written in response to this interrupt will cause at least two Flags to be transmitted between frames.
> 0 | 0 | The byte in the receiver buffer is 8 bits.
> 1 | The byte in the receiver buffer is less than 8 bits.

> Table 12-14. Serial Port Control Register Ports A and B
> Serial Port x Control Register (SACR) (Address = 0xC4) (SBCR) (Address = 0xD4)
> Bit(s) | Value | Description
> 7:6 | 00 | No operation. These bits are ignored in the Async mode.
> | 01 | In clocked serial mode, start a byte receive operation.
> | 10 | In clocked serial mode, start a byte transmit operation.
> | 11 | In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously.
> 5:4 | 00 | Parallel Port C is used for input.
> | 01 | Parallel Port D is used for input.
> | 1x | Disable the receiver input.
> 3:2 | 00 | Async mode with 8 bits per character.
> | 01 | Async mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data.
> | 10 | Clocked serial mode with external clock.
> | 11 | Clocked serial mode with internal clock.
> 1:0 | 00 | The Serial Port interrupt is disabled.
> | 01 | The Serial Port uses Interrupt Priority 1.
> | 10 | The Serial Port uses Interrupt Priority 2.

> Table 12-15. Serial Port Control Register Ports C and D
> Serial Port x Control Register (SCCR) (Address = 0xE4) (SDCR) (Address = 0xF4)
> Bit(s) | Value | Description
> 7:6 | 00 | No operation. These bits are ignored in the async mode.
> 01 | In clocked serial mode, start a byte receive operation.
> 10 | In clocked serial mode, start a byte transmit operation.
> 11 | In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously.
> 5 | 0 | Enable the receiver input.
> 1 | Disable the receiver input.
> 4 | x | This bit is ignored.
> 3:2 | 00 | 8 bits per character.
> 01 | 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data.
> 10 | Clocked serial mode with external clock.
> 11 | Clocked serial mode with internal clock.
> 1:0 | 00 | The serial port interrupt is disabled.
> 01 | The serial port uses Interrupt Priority 1.
> 10 | The serial port uses Interrupt Priority 2.
> 11 | The serial port uses Interrupt Priority 3.

> Table 12-16. Serial Port Control Register Ports E and F
> Serial Port x Control Register (SECR) (Address = 0xCC) (SFCR) (Address = 0xDC)
> Bit(s) | Value | Description
> 7:6 | 00 | No operation. These bits are ignored in the Async mode.
> 01 | In HDLC mode, force receiver in Flag Search mode.
> 10 | No operation.
> 11 | In HDLC mode, transmit an Abort pattern.
> 5 | 0 | Enable the receiver input.
> 1 | Disable the receiver input.
> 4 | x | This bit is ignored.
> 3:2 | 00 | Async mode with 8 bits per character.
> 01 | Async mode with 7 bits per character. In this mode the most significant bit of a byte is ignored for transmit, and is always zero in receive data.
> 10 | HDLC mode with external clock. The external clock is supplied via Serial Port F pins.
> 11 | HDLC mode with internal clock. The clock is 16X the data rate, and the DPLL is used to recover the receive clock. If necessary, the receiver and transmitter clocks can be output via Port F pins.
> 1:0 | 00 | The serial port interrupt is disabled.
> 01 | The serial port uses Interrupt Priority 1.
> 10 | The serial port uses Interrupt Priority 2.
> 11 | The serial port uses Interrupt Priority 3.

> Table 12-17. Extended Register Asynchronous Mode All Ports
> Serial Port x Extended Register (SAER) (Address = 0xC5) (SBER) (Address = 0xD5) (SCER) (Address = 0xE5) (SDER) (Address = 0xF5) (SEER) (Address = 0xCD) (SFER) (Address = 0xDD)
> Bit(s) | Value | Description (Async mode only)
> 7:5 | xxx | These bits are ignored in async mode.
> 4 | 0 | Normal async data encoding.
> 1 | Enable RZI coding (3/16ths bit cell IRDA-compliant).
> 3 | 0 | Normal Break operation. This option should be selected when address bits are expected.
> 1 | Fast Break termination. At the end of Break a dummy character is written to the buffer, and the receiver can start character assembly after one bit time.
> 2 | 0 | Async clock is 16X data rate.
> 1 | Async clock is 8X data rate.
> 1:0 | xx | These bits are ignored in async mode.

> Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only)
> Serial Port x Extended Register (SAER) (Address = 0xC5) (SBER) (Address = 0xD5) (SCER) (Address = 0xE5) (SDER) (Address = 0xF5)
> Bit(s) | Value | Description (Clocked serial mode only)
> 7 | 0 | Normal clocked serial operation.
> 1 | Timer synchronized clocked serial operation.
> 6 | 0 | Timer-synchronized clocked serial uses Timer B1.
> 1 | Timer-synchronized clocked serial uses Timer B2.
> 5:4 | 00 | Normal clocked serial clock polarity, inactive High. Internal or external clock.
> 01 | Normal clocked serial clock polarity, inactive Low. Internal clock only.
> 10 | Inverted clocked serial clock polarity, inactive Low. Internal or external clock.
> 11 | Inverted clocked serial clock polarity, inactive High. Internal clock only.
> 3:2 | xx | These bits are ignored in clocked serial mode.
> 1 | 0 | No effect on transmitter.
> 1 | Terminate current clocked serial transmission. No effect on buffer.
> 0 | 0 | No effect on receiver.
> 1 | Terminate current clocked serial reception.

> Table 12-19. Extended Register HDLC Mode (Ports E and F only)
> Serial Port x Extended Register (SEER) (Address = 0xCD) (SFER) (Address = 0xDD)
> Bit(s) | Value | Description (HDLC mode only)
> 7:5 | 000 | NRZ data encoding for HDLC receiver and transmitter.
> 010 | NRZI data encoding for HDLC receiver and transmitter.
> 100 | Biphase-Level (Manchester) data encoding for HDLC receiver and transmitter.
> 110 | Biphase-Space data encoding for HDLC receiver and transmitter.
> 111 | Biphase-Mark data encoding for HDLC receiver and transmitter.
> 4 | 0 | Normal HDLC data encoding.
> 1 | Enable RZI coding (1/4th bit cell IRDA-compliant). This mode can only be used with internal clock and NRZ data encoding.
> 3 | 0 | Idle line condition is Flags.
> 1 | Idle line condition is all ones.
> 2 | 0 | Transmit Flag on underrun.
> 1 | Transmit Abort on underrun.
> 1:0 | xx | These bits are ignored in HDLC mode.

> ### 12.3 Serial Port Interrupt

> A common interrupt vector is used for the receive and transmit interrupts. There is a separate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3. When an interrupt is requested, it will take place immediately when priorities allow and an instruction execution is complete. The interrupt is lost if the request flip-flop is cleared before the interrupt takes place. If the flip-flop is not cleared in the interrupt, another interrupt will take place when priorities are lowered.

> Figure 12-3. Generation of Serial Port Interrupts

> The receive interrupt request flip-flop is set after the stop bit is sampled on receive, nominally 1/2 of the way through the stop bit. Data bits are transferred on this same clock from the receive shift register to the receive data register.

> The transmit interrupt request flip-flop is set on the leading edge of the stop bit for data register empty and at the trailing edge of the stop bit for shift register empty (transmitter idle). Unless the data register is empty on this trailing edge of the stop bit, the transmitter does not become idle. The transmitter becomes idle only if the data register is empty at the trailing edge of the stop bit.

> The serial port interrupt vectors are shown in Table 6-1.

> ### 12.4 Transmit Serial Data Timing

> On transmit, if the interrupts are enabled, an interrupt is requested when the transmit register becomes empty and, in addition, an interrupt occurs when the shift register and transmit register both become empty, that is, when the transmitter becomes idle. The shift register is empty when the last bit is shifted out. When the transmit data register contains data and the shift register finishes sending data, the data bits are clocked from the transmit register to the shift register, and the shift register is never idle. The interrupt request is cleared either by writing to the data register or by writing to the status register (which does not affect the status register). The data register normally is clocked into the shift register each time the shift register finishes sending data, leaving the data register empty. This causes an interrupt request. The interrupt routine normally answers the interrupt before the shift register runs dry (9 to 11 baud clocks, depending on the mode of operation). The interrupt routine stores the next data item in the data register, clearing the interrupt request and supplying the next data bits to be sent. When all the characters have been sent, the interrupt service routine answers the interrupt once the data register becomes empty. Since it has no more data, it clears the interrupt request by storing to the status register. At this point the routine should check if the shift register is empty; normally it won't be. If it is, because the interrupt was answered late, the interrupt routine should do any final cleanup and store to the status register again in case the shift register became empty after the pending interrupt is cleared. Normally, though, the interrupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers, as in the case for RS-485 transmission.

> ### 12.5 Receive Serial Data Timing

> When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register. After 7 or 8 data bits have been received, the next bit will be either a 9th (8th) address bit, or a stop bit will be sampled. If the Rx line is low, it is an address bit and the address bit received bit in the status register will be enabled. If an address bit is detected, the receiver will attempt to sample the stop bit. If the line is high when sampled, it is a stop bit and a new scan for a new start bit will begin after the sample point. At the same time, the data bits are transferred into the receive data register and an interrupt, if enabled, is requested.

> On receive, an interrupt is requested when the receiver data register has data. This happens when data bits are transferred from the receive shift register to the data register. This also sets bit 7 of the status register. The interrupt request and bit 7 are cleared when the data register is read.

> An interrupt is requested if bit 7 is high. The interrupt is requested on the edge of the transmitter data register becoming empty or the transmitter shift register becoming empty. The transmitter interrupt is cleared by writing to the status register or to the data register.

> On receive, the scan for the next start bit starts immediately after the stop bit is detected. The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit. If there is a 9th (8th) address bit, the stop bit follows that bit.

> The serial clock can be configured to be either 16× the data rate or 8× the data rate.

> Figure 12-4. Serial Port Synchronization

> ### 12.6 Clocked Serial Ports

> Ports A-D can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received first. By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock. The serial port can generate the clock or the clock can be provided externally.

> The clock polarity is programmable in clocked serial mode according to Figure . The clocked serial transfer may also be synchronized to the output of either of the match conditions in Timer B to give precisely timed transfers.

> To enable the clocked serial mode, a code must be in bits (3,2) of the control register, enabling the clocked serial mode with either an internal clock or an external clock. The transition between the external and the internal clock should be performed with care. Normally a pullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock.

> Figure 12-5. Clock Polarities Supported in Clocked Serial Mode

> In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications. However, to initiate basic sending or receiving, a command must be issued by writing to bits (7,6) of the control register for each byte sent or received. One command is for sending a byte, a different command is for receiving a byte, and yet another command can initiate a transmit and receive at the same time for full duplex communication. Alternatively, a read or write to the Serial Ports A-D Address registers (SxAR) eliminates the need to issue separate receive and transmit commands. In clocked serial mode, reading the data from the corresponding SxAR register automatically causes the receiver to start a byte receive operation, eliminating the need for software to issue the Start Receive command. Any data contained in the receive buffer will be read first before being replaced with new incoming data. Similarly, writing the data to the SxAR register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock.

> To transmit in internal clock mode, the user must first load the data register (which must be empty) and then store the send code. When the shift register finishes sending the current character, if any, the data register will be loaded into the shift register and transmitted by an 8-clock burst. One character can be in the process of transmitting while another character is waiting in the data register tagged with the send code. The send code is effectively double-buffered.

> To receive a character in internal clock mode, the receive shift register should be idle. The user then stores the receive code in the control register. A burst of 8 clocks will be generated and the sender must detect the clocks and shift output data to the data line on the falling edge of each clock. The receiver will sample the data on the rising edge of each clock for clock modes 00 and 01 or the falling edge for clock modes 10 and 11. The receive mode cannot double-buffer characters when using the internal clock. The shift register must be idle before another character receive can be initiated. However, the interrupt request and character ready takes place on the rising edge of the last clock pulse. If the next receive code is stored before the natural location of the next falling edge, another receive will be initiated without pausing the clock. To do this, the interrupt has to be serviced within 1/2 clock.

> To transmit each byte in external clock mode, the user must load the data register and then store the send code. When the shift register is idle and the receiver provides a clock burst, the data bits are transferred to the shift register and are shifted out. Once the transfer is made to the shift register, a new byte can be loaded into the transmit register and a new send code can be stored.

> To receive a byte in external clock mode, the user must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register. Since the receive code must be stored before the transmitter sends the next byte, the receiver must service the interrupt within 1/2 baud clock to maintain full-speed transmission. This is usually not practical unless a flow control arrangement is made or the transmitter inserts gaps between the clock bursts.

> In order to carry on high-speed communication, the best arrangement will usually be for the receiver to provide the clock. When the receiver provides the clock, the transmitter should always be able to keep up because it is double-buffered and has a full character time to answer the transmitter data register empty interrupt. The receiver will answer interrupts that are generated on the last clock rising edge. If the interrupt can be serviced within 1/2 clock, there will be no pause in the data rate. If it takes the receiver longer to answer, then there will be a gap between bytes, the length of which depends on the interrupt latency. For example, if the baud rate is 400,000 bps, then up to 50,000 bytes per second could be transmitted, or a byte every 20 µs. No data will be lost if the transmitter can answer its interrupts within 20 µs. There will be no slow down if the receiver can answer its interrupt within 1/2 clock or 1.25 µs. If it can answer within 1.5 clocks, or 2.75 µs, the data rate will slow to 44,444 bytes per second. If it can answer in 2.5 clocks or 6.25 µs, the data rate slows to 40,000 bytes per second. If it can answer in 3.5 clocks or 8.75 µs, the data rate will slow to 36,363 bytes per second, and so forth.

> If two-way half-duplex communication is desired, the clock can be turned around so that the receiver always provides the clock. This is slightly more complicated since the receiver cannot initiate a message. If the receiver attempts to receive a character and the transmitter is not transmitting, the last bit sent will be received for all eight bits.

> ### 12.7 Clocked Serial Timing

> ### 12.7.1 Clocked Serial Timing With Internal Clock

> For synchronous serial communication, the serial clock can be either generated by the Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied to both full-duplex and half-duplex clocked serial communication where the serial clock is generated internally by the Rabbit. Other SPI compatible clock modes supported by the Rabbit 3000 are shown in Figure 12-5. With an internal clock, the maximum serial clock rate is `perclk`/4.

> Figure 12-6. Full-Duplex Clocked Serial Timing Diagram with Internal Clock (Mode 00)

> ### 12.7.2 Clocked Serial Timing with External Clock

> In a system where the Rabbit serial clock is generated by an external device, the clock signal has to be synchronized with the internal peripheral clock (`perclk`) before data can be transmitted or received by the Rabbit. Depending on when the external serial clock is generated, in relation to `perclk`, it may take anywhere from 2 to 3 clock cycles for the external clock to be synchronized with the internal clock before any data can be transferred. Figure 12-7 shows the timing relationship among `perclk`, the external serial clock, and data transmit.

> Figure 12-7. Synchronous Serial Data Transmit Timing with External Clock (Mode 00)

> Figure 12-8 shows the timing relationship among `perclk`, the external serial clock, and data receive. Note that RxA is sampled by the rising edge of `perclk`.

> Figure 12-8. Synchronous Serial Data Receive Timing with External Clock (Mode 00)

> When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit `perclk`. If we sum the maximum number of `perclk` cycles required to perform clock synchronization for each of the receive and transmit cases, then the fastest external serial clock frequency would be limited to `perclk`/6.

> ### 12.8 Synchronous Communications on Ports E and F

> Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead. An interrupt is generated whenever at least one byte is available in the receiver buffer and every time a byte is removed from the transmitter buffer.

> Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3. In asynchronous mode this clock can be either sixteen (the default) or eight times the data rate. In HDLC mode this clock is sixteen times the data rate. Note that the fastest output from Timer A2 or A3 is the same frequency as the peripheral clock. Thus the maximum data rate is the peripheral clock frequency divided by eight in async mode and divided by sixteen in HDLC mode.

> The HDLC receiver employs a Digital Phase-Locked-Loop (DPLL) to generate a synchronized receive clock for the incoming data stream. HDLC mode also allows for an external 1x (same speed as the data rate) clock for both the receiver and the transmitter. HDLC receive and transmit clocks can be input or output, as appropriate, via the specified pins. When using an external clock, the maximum data rate is one-sixth of the peripheral clock rate.

> In asynchronous mode the port can send and receive seven or eight bits and has the option of appending and recognizing an additional address bit. On transmit, the address bit is automatically appended to the data when this data is written to the address register or long stop register. Writing to the address register appends an "zero" address bit to the data, while writing to the long stop register appends an "one" address bit to the data. The address bit is followed by a normal stop bit. Normal data is written to the data register to be transmitted. On receive, a status bit distinguishes normal data from "address" data. This status bit is set to one if a "zero" address bit is received. In non-address bit applications, this indicates a framing error. This status bit can also indicate a received break, if the accompanying data is all zeros (this is the definition of break). Asynchronous mode operates full-duplex. Either the receive data available, transmit buffer empty or transmit idle conditions can be programmed to generate an interrupt.

> The HDLC mode allows full-duplex synchronous communication. Either an internal or external clock may be selected for both the receiver and the transmitter. HDLC mode encapsulates data within opening and closing Flags, and sixteen bits of CRC precedes the closing Flag. All information between the opening and closing Flag is "zero-stuffed". That is, if five consecutive ones occur, independent of byte boundaries, a zero is automatically inserted by the transmitter and automatically deleted by the receiver. This allows a Flag byte (07Eh) to be unique within the serial bit stream. The standard CRC-CCITT polynomial (x16 + x12 + x5 + 1) is implemented, with the generator and checker preset to all ones.

> Both receive and transmit operation are essentially automatic. In the receiver, each byte is marked with status to indicate end-of-frame, short frame and CRC error. The receiver automatically synchronizes on Flag bytes and presets the CRC checker appropriately. If the current receive frame is not needed (because it is addressed to a different station, for example) a Flag Search command is available. This command forces the receiver to ignore the incoming data stream until another Flag is received. In the transmitter, the CRC generator is preset and the opening Flag is transmitted automatically after the first byte is written to the transmitter buffer, and CRC and the closing flag are transmitted after the byte that is written to the buffer through the Address Register. If no CRC is required, writing the last byte of the frame to the Long Stop Register automatically appends a closing flag after the last byte. If the transmitter underflows, either an Abort or a Flag will be transmitted, under program control. A command is available to send the Abort pattern (seven consecutive ones) if a transmit frame needs to be aborted prematurely. The Abort command takes effect on the next byte boundary, and causes the transmission of an FEh (a zero followed by seven ones), after which the transmitter will send the idle line condition. The Abort command also purges the transmit FIFO. The idle line condition may be either Flags or all ones.

> Both the receiver and transmitter contain four bytes of buffering for the data. Status bits are buffered along with the data in both receiver and transmitter. The receiver automatically generates an interrupt at the end of a received frame, and the transmitter generates an interrupt at the end of CRC transmission, at the end of the transmission of an Abort sequence, and at the end of the transmission of a closing Flag.

> The transmitter is not capable of sending an arbitrary number of bits, but only a multiple of bytes. However, the receiver can receive frames of any bit length. If the last "byte" in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software can then use the table below to determine the number of valid data bits in this last "byte." Note that the receiver transfers all bits between the opening and closing Flags, except for the inserted zeros, to the receiver data buffer.

> Last Byte Bit Pattern | Valid Data Hits
> bbbbbbb0 | 7
> bbbbbb01 | 6
> bbbbb011 | 5
> bbbb0111 | 4
> bbb01111 | 3
> bb011111 | 2
> b0111111 | 1

> Several types of data encoding are available in the HDLC mode. In addition to the normal NRZ, they are NRZI, Biphase-Level (Manchester), Biphase-Space (FM0) and Biphase-Mark (FM1). Examples of these encodings are shown in the Figure below. Note that in NRZI, Biphase-Space and Biphase-Mark the signal level does not convey information. Rather it is the placement of the transitions that determine the data. In Biphase-Level it is the polarity of the transition that determines the data.

> In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that uses the timing of the transitions on the receive data stream to adjust its count. The DPLL adjust the count so that the output of the DPLL will be properly placed in the bit cells to sample the receive data. To work properly, then, transitions are required in the receive data stream. NRZ data encoding does not guarantee transitions in all cases (a long string of zeros for example), but the other data encodings do. NRZI guarantees transitions because of the inserted zeros, and the Biphase encodings all have at least one transition per bit cell.

> The DPLL counter normally counts by sixteen, but if a transition occurs earlier or later than expected the count will be modified during the next count cycle. If the transition occurs earlier than expected, it means that the bit cell boundaries are early with respect to the DPLL-tracked bit cell boundaries, so the count is shortened, either by one or two counts. If the transition occurs later than expected, it means that the bit cell boundaries are late with respect to the DPLL-tracked bit cell boundaries, so the count is lengthened, either by one or two counts. The decision to adjust by one or by two depends on how far off the DPLL-tracked bit cell boundaries are. This tracking allows for minor differences in the transmit and receive clock frequencies.

> With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts after every receive data transition. Since NRZ encoding does not guarantee a minimum density of transitions, the difference between the sending data rate and the DPLL output clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guarantees at least one transition every six bits (with the inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/48 (~2%).

> With Biphase data encoding (either -Level, -Mark or -Space), the DPLL runs only as long as transitions are present in the receive data stream. Two consecutive missed transitions causes the DPLL to halt operation and wait for the next available transition. This mode of operation is necessary because it is possible for the DPLL to lock onto the optional transitions in the receive data stream. Since they are optional, they will eventually not be present and the DPLL can attempt to lock onto the required transitions. Since the DPLL can adjust by one count every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/16 (~6%).

> With Biphase data encoding the DPLL is designed to work in multiple-access conditions where there may not be Flags on an idle line. The DPLL will properly generate an output clock based on the first transition in the leading zero of an opening Flag. Similarly, only the completion of the closing Flag is necessary for the DPLL to provide the extra two clocks to the receiver to properly assemble the data. In Biphase-Level mode, this means the transition that defines the last zero of the closing Flag. In Biphase-Mark and Biphase-Space modes this means the transition that defines the end of the last zero of the closing Flag.

> The figure below shows the adjustment ranges and output clock for the different modes of operation of the DPLL. Each mode of operation will be described in turn.

> With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bit-cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the "add one" and "add two" regions shown. If a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to shorten the count to line up the bit-cell boundaries. This corresponds to the "subtract one" and "subtract two" regions shown. The DPLL makes no adjustment if the bit-cell boundaries are lined up within one count of the divide-by-sixteen counter. The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up.

> With Biphase-Level encoding there is a guaranteed "clock" transition at the center of every bit cell and optional "data" transitions at the bit cell boundaries. The DPLL only uses the clock transitions to track the bit cell boundaries, by ignoring all transitions occurring outside a window around the center of the bit cell. This window is half a bit-cell wide. Additionally, because the clock transitions are guaranteed, the DPLL requires that they always be present. If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters the search mode. Search mode assumes that the next transition seen is a clock transition and immediately synchronizes to this transition. No clock output is provided to the receiver during the search operation. Decoding Biphase-Level data requires that the data be sampled at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter point to sample the data.

> Biphase-Mark and Biphase space encoding are identical as far as the DPLL is concerned, and are similar to Biphase-Level. The primary difference is the placement of the clock and data transitions. With these encodings the clock transitions are at the bit-cell boundary and the data transitions are at the center of the bit cell, and the DPLL operation is adjusted accordingly. Decoding Biphase-Mark or Biphase-Space encoding requires that the data be sampled by both edges of the recovered receive clock.
> An optional IRDA (Infrared Data Association) -compliant encode and decode function is available in both asynchronous mode and HDLC mode. The encoder sends an active-High pulse for a zero and no pulse for a one. In the asynchronous 16x mode this pulse is 3/16ths of a bit cell wide, while in the asynchronous 8x mode it is 1/8th of a bit cell wide. In HDLC mode the pulse is 1/4th of a bit cell wide. In all modes the decoder watches for active-Low pulses, which are stretched to one bit time wide to recreate the normal asynchronous waveform for the receiver. Enabling the IRDA-compliant encode/decode modifies the transmitter in HDLC mode so that there are always two opening Flags transmitted.

> ### 12.9 Serial Port Software Suggestions

> The receiver and transmitter share the same interrupt vector, but it is possible to make the receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt to either of two different routines. This is desirable to make the ISR less complex and to reduce the interrupt off time. No interrupts will be lost since distinct interrupt flip-flops exist for receive and transmit. The dispatcher can test the receiver data register full bit to dispatch. If this bit is on, the interrupt is dispatched for receive, otherwise for transmit. The receiver receives first consideration because it must be serviced attentively or data could be lost.

> The dispatcher might look as follows.

>     interrupt:

>     push af          ; 10
>     ioi ld a,(SCSR)  ; 7 get status register serial port C
>     jp m,receive     ; 7 go service the receive interrupt
>                        ;    else service transmit interrupt

> The individual interrupts would assume that register AF has been saved and the status register has been loaded into Register A.

> The interrupt service routines can, as a matter of good practice and obtaining optimum performance, remove the cause of the interrupt and re-enable the interrupts as soon as possible. This keeps the interrupt latency down and allows the fastest transmission speed on all serial ports.

> All the serial ports will normally generate priority level 1 interrupts. In exceptional circumstances, one or more serial ports can be configured to use a higher priority interrupt. There is an exception to be aware of when a serial port has to operate at an extremely high speed. At 115,200 bps, the highest speed of a PC serial port, the interrupts must be serviced in 10 baud times, or 86 µs, in order not to lose the received characters. If all six serial ports were operating at this receive speed, it would be necessary to service the interrupt in less than 21.5 µs to assure no lost characters. In addition, the time taken by other interrupts of equal or higher priority would have to be considered. A receiver service routine might appear as follows below. The byte at `bufptr` is used to address the buffer where data bits are stored. It is necessary to save and increment this byte because characters could be handled out of order if two receiver interrupts take place in quick succession.

>     receive:

>     push hl         ; 10 save hl
>     push de         ; 10 save de
>     ld hl,struct    ; 6
>     ld a,(hl)       ; 5 get in-pointer
>     ld e,a          ; 2 save in pointer in e
>     inc hl          ; 2 point to out-pointer
>     cmp a,(hl)      ; 5 see if in-pointer=out-pointer (buffer full)
>     jr z,roverrun   ; 5 go fix up receiver over run
>     inc a           ; 2 incement the in pointer
>     and a,mask      ; 4 mask such as 11110000 if 16 buffer locs
>     dec hl          ; 2
>     ld (hl),a       ; 6 update the in pointer
>     ioi ld a,(SCDR) ; 11 get data register port C, clears interrupt request
>     ipres	            ; 4 restore the interrupt priority

>     ; 68 clocks to here
>     ; to level before interrupt took place
>     ; more interrupts could now take place,
>     ; but receiver data is in registers
>     ; now handle the rest of the receiver interrupt routine
>     ld hl,bufbase   ; 6
>     ld d,0          ; 6
>     add hl,de       ; 2 location to store data
>     ld (hl),a       ;  6 put away the data byte
>     pop de          ;7
>     pop hl          ; 7
>     pop af          ; 7
>     ret             ; 8 from interrupt

>     ; 117 clocks to here

> This routine gets the interrupts turned on in about 68 clocks or 3.5 µs at a clock speed of 20 MHz. Although two characters may be handled out of order, this will be invisible to a higher level routine checking the status of the input buffer because all the interrupts will be completed before the higher level routine can perform a check on the buffer status.

> A typical way to organize the buffers is to have an in-pointer and an out-pointer that increment through the addresses in the data buffer in a circular manner. The interrupt routine manipulates the in-pointer and the higher level routine manipulates the out-pointer. If the in-pointer equals the out-pointer, the buffer is considered full. If the out-pointer plus 1 equals the in-pointer, the buffer is empty. All increments are done in a circular fashion, most easily accomplished by making the buffer a power of two in length, then anding a mask after the increment. The actual memory address is the pointer plus a buffer base address.

> ### 12.9.1 Controlling an RS-485 Driver and Receiver

> RS-485 uses a half-duplex method of communication. One station enables its driver and sends a message. After the message is complete, the station disables the driver and listens to the line for a reply. The driver must be enabled before the start bit is sent and not disabled until the stop bit has been sent. The transmitter idle interrupt is normally used to disable the RS-485 driver and possibly enable the receiver.

> ### 12.9.2 Transmitting Dummy Characters

> It may be desired to operate the serial transmitter without actually sending any data. "Dummy" characters are transmitted to pass time or to measure time.

> The output of the transmitter may be disconnected from the transmitter output pin by manipulating the control registers for Parallel Port C or D, which are used as output pins. For example, if Serial Port B is to be temporarily disconnected from its output pin, which is bit 4 of Parallel Port C, this can be done as follows.

> 1. Store a "1" in bit 4 of the parallel port data output register to provide the quiescent state of the drive line.

> 2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of course, this should not be done until the transmitter is idle.

> A similar procedure can be used if the serial port is set up to use alternate output pins on port D. Only Serial Ports A and B can use alternate outputs on Parallel Port D.

> If an RS-485 driver is being used, dummy characters can be transmitted by disabling the driver after the stop bit has been sent. This is an alternative to the above procedure.

> ### 12.9.3 Transmitting and Detecting a Break

> A break is created when the output of the transmitter is driven low for an extended period. If a break is received, it will appear as a series of characters filled with zeros and with the 9th bit detected low. This could only be confused with a legitimate message if a protocol using the 9th bit was in effect. Break is not usually used as a message in such protocols.

> A break can be transmitted by transmitting a byte of zeros at a very slow baud rate. Another and probably better method is to disconnect the transmitter from the output pin, and use the parallel port bit to set the line low while sending dummy characters to time out the break.

> The use of break as a signaling device should be avoided because it is slow, erratically supported by different types of hardware, and usually creates more problems than it solves.

> ### 12.9.4 Using A Serial Port to Generate a Periodic Interrupt

> A serial port may be used to generate a periodic interrupt by continuously transmitting characters. Since the Tx output via Parallel Port C or D can be disabled, the transmitted characters are transmitted to nowhere. Because the character output path is double-buffered, there will be no gaps in the character transmission, and the interrupts will be exactly periodic. The interrupts can happen every 9, 10 or 11 baud times, depending on whether 7 or 8 bits are transmitted and on whether the 9th (8th) bit is sent.

> ### 12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes

> Some systems may require two stop bits. In some cases, it may be necessary to send a parity bit. Certain systems, such as some 8051-based multidrop communications systems, use a 9th data bit to mark the start of a message frame. The Rabbit 3000 can receive parity or message formats that contain a 9th bit without problem. Transmitting messages with parity or messages that always contain a 9th bit is also possible. It is quite easy to do so for byte formats that use only 7 data bits, in which case the 9th bit or parity bit is actually an 8th bit. Sending a 9th low bit is supported by hardware. Sending a 9th bit as a high value requires a write to the Serial Port A-F Long Stop Register (SxLR) which is the same as two stop bits.

> Figure 12-9 illustrates the standard asynchronous serial output patterns.

> Figure 12-9. Asynchronous Serial Output Patterns

> ### 12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters

> If only 7 data bits are being sent, sending an additional parity or signal bit is easily solved by sending 8 bits and always setting bit 7 (the eighth bit) of the byte to "1" or "0" depending on what is desired. No special precautions are needed if two stop bits are to be received. If parity is received with 7 data bits, receive the data as 8 bits, and the parity will be in the high bit of the byte.

> ### 12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters

> In order to receive parity with 8 data bits, a check is made on each character for a 9th bit low. The 9th bit, or parity bit, is low if bit 6 of the serial port status register (SxSR) is set to a "1" after the character is received. If the 9th bit is not a zero, then the serial port treats it as an extra stop bit. So if the 9th bit low flag is not set, it should be assumed that the parity bit is a "1."

> Setting the 9th bit high or low can easily be done in the Rabbit 3000. The 9th bit can be set low by a write to the Serial Port A-F Address Register (SxAR) and the 9th bit can be set high by a write to the Serial Port A-F Long Stop Register (SxLR).

> ### 12.9.8 Supporting 9th Bit Communication Protocols

> This section describes how 9th bit communication protocols work. 9th bit communication protocols are supported by processors such as the 8051 and the Z180, and by companies such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a parity bit would normally be placed. Requests from the network master to one of its slaves consist of a frame of bytes--the first byte has the 9th bit set to "1" (as the signal is observed at the Tx pin of the processor) and the following bytes have the 9th bit set to "0." The first byte is identified as the address byte, which specifies the slave unit where the message is directed. This enables a slave to find the start of a message, which is the byte with the 9th bit set, and to determine if the message is directed to it. If the message is directed to a particular slave, the slave will then read the characters in the rest of the message; otherwise the slave will continue to scan for a start of message character containing its address.

> Normally the 9th bit is set to "1" only on the first byte of a request transmitted by the network master. The subsequent bytes and the slave replies have the 9th bit set to zero. Since the majority of the traffic has a 9th bit set low, it is only necessary to stretch the stop bit for the first bytes or address bytes. This can be done without sacrificing performance by sending a dummy character (transmitter disconnected) after the address byte.

> Some microprocessor serial ports have a "wake up" mode of operation. In this mode, characters without the 9th bit set to "1" are ignored, and no interrupt is generated. When the start of a frame is detected, an interrupt takes place on that byte. If the byte contains the address of the slave, then the "wake up" mode is turned off so that the remaining characters in the frame can be read. This scheme reduces the overhead associated with messages directed to other slaves, but it does not really help with the worst-case load. In most cases, the worst-case compute load is the governing factor for embedded systems. In addition, it is quite easy for the interrupt driver to dismiss characters not directed to the system. For these reasons, the "wake up" mode was not implemented for the Rabbit.

> The 9th bit protocols suffer from a major problem that the IBM-PC uarts can support the 9th bit only by using special drivers.

> ### 12.9.9 Rabbit-Only Master/Slave Protocol

> If only Rabbit microprocessors are connected, the 9th bit low can be set on the address byte, and the remaining bytes can be transmitted in the normal 8-bit mode. This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times; the remaining bytes are transmitted in 10 baud times.

> ### 12.9.10 Data Framing/Modbus

> Some protocols, for example, Modbus, depend on a gap in the data frame to detect the beginning of the next frame. The 9th bit protocol is another way to detect the start of a data frame.

> The Modbus protocol requires that data frames begin with a minimum 3.5-character quiet time. The receiver uses this 3.5-character gap to detect the start of a frame. In order for the receiving interrupt service routine to detect this gap, it is suggested that dummy characters be transmitted to help detect the gap. This can be done in the following manner. The transmitter starts transmitting dummy characters when the first character interrupt is received. Each time there is an interrupt, either receiver data register full or transmitter data register empty, a dummy character is transmitted if the transmitter data register is empty. Although the transmitter and receiver operate at approximately the same baud rate, there can be a difference of up to about 5% between their baud rates. Thus the receiver full and transmitter empty interrupts will become out of phase with each other, assuming that the remote station transmits without gaps between characters. A counter is zeroed each time a character is received, and the counter is incremented each time a character is transmitted. If this counter holds (n), this indicates that a gap has been detected in the frame; the length of the gap is (n - 1) to (n) characters. The start of frame could be marked by (n) reaching 3, indicating that the existence of a gap at least two characters long.

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