Smart Star User's Manual

> ## Appendix C. Power Management

> Appendix C provides information on the current requirements of the Smart Star I/O cards, the use and installation of a backup battery, and some background on power mangement.

> ### C.1 Current Requirements

> Remember to take the current draw of the various I/O cards into consideration when selecting the power supply for your Smart Star control system.

> Table C-1 lists the typical current consumption for the CPU card and the I/O cards.

> Table C-1. Current Consumption of I/O Cards Attached to Smart Star Backplane
> I/O Cards | Current Consumption
> +5 V Supply | +V_USER Supply
> Digital I/O (SR9200 series) | 65 mA | up to 200 mA/output1
> A/D Converter (SR9300 series) D/A Converter (SR9400 series) | 40 mA | 35 mA
> Relay (SR9500 series) | 10 mA | 75 mA
> CPU card | 190 mA | --

> 1 Maximum current 2.0 A per I/O card, 7.0 A for Smart Star system

> ### C.2 Batteries and External Battery Connections

> An onboard 265 mA·h lithium coin cell on the CPU card provides power to the real-time clock and SRAM when external power is removed from the Smart Star control system. This allows the CPU card to continue to keep track of time and preserves the SRAM memory contents while the power is off.

> The drain on the battery is typically less than 20 µA when there is no external power applied. The battery can last

> The drain on the battery is typically less than 4 µA when external power is applied. The battery can last for

> Since the shelf life of the battery is 10 years, the battery can last for most of its shelf life when external power is applied most of the time.

> #### C.2.1 Replacing the Backup Battery

> The battery is user-replaceable, and is fitted in a battery holder. To replace the battery, lift up on the spring clip and slide out the old battery. Use only a Panasonic CR2330 or equivalent replacement battery, and insert it into the battery holder with the + side facing up.

> NOTE | The SRAM contents and the real-time clock settings will be lost if the battery is replaced with no power applied to the Smart Star. There is a provision for an external battery if you need to save the SRAM contents and the real-time clock settings since the CPU card needs to be removed from the backplane in order to change the onboard battery.
> NOTE | There is an explosion danger if the battery is short-circuited, recharged, or replaced incorrectly. Replace the battery only with the same type or an equivalent type recommended by the battery manufacturer. Dispose of used batteries according to the battery manufacturer's instructions.

> #### C.2.2 Battery-Backup Circuit

> Figure C-1 shows the battery-backup circuit.

> Figure C-1. Smart Star CPU Card Backup Battery Circuit

> The battery-backup circuit serves three purposes:

> - It reduces the battery voltage to the SRAM and to the real-time clock, thereby limiting the current consumed by the real-time clock and lengthening the battery life.

> - It ensures that current can flow only out of the battery to prevent charging the battery.

> - A voltage, VOSC, is supplied to U14, which keeps the 32.768 kHz oscillator working when the voltage begins to drop.

> VRAM and Vcc are nearly equal (<100 mV, typically 10 mV) when power is supplied to the CPU card.

> #### C.2.3 Power to VRAM Switch

> The VRAM switch, shown in Figure C-2, allows the battery backup to provide power when the external power goes off. The switch provides an isolation between +5 V and the battery when +5 V goes low. This prevents the +5 V line from draining the battery.

> Figure C-2. VRAM Switch

> Transistor Q6 is needed to provide a very small voltage drop between +5 V and VRAM (<100 mV, typically 10 mV) so that the processor lines powered by +5 V will not have a significantly different voltage than VRAM.

> When the CPU card is not resetting (pin 2 on U4 is high), the /RES line will be high. This turns on Q6, causing its collector to go low. This turns on Q7, allowing VRAM to nearly equal +5 V.

> When the CPU card is resetting, the /RES line will go low. This turns off Q6 and Q7, providing an isolation between +5 V and VRAM.

> The battery-backup circuit keeps VRAM from dropping below 2 V.

> #### C.2.4 Reset Generator

> The CPU card uses a reset generator, U4, to reset the Rabbit 2000 microprocessor when the voltage drops below the voltage necessary for reliable operation. The reset occurs between 4.50 V and 4.75 V, typically 4.63 V.

> #### C.2.5 External Battery

> A connection for an external backup battery is provided at header J8, shown in Figure C-3. The header is wired to provide reverse polarity protection.

> Figure C-3. External Backup Battery Connection

> The external battery connection is useful if the SRAM and real-time clock data need to be preserved while the backup battery is being changed. This way power can continue to be applied to the CPU card from the backplane (if the external backup battery is being replaced) or from the external battery (if the onboard backup battery needs to be changed since this requires removing the CPU card from the backplane in order to access the onboard backup battery).

> ### C.3 Chip Select Circuit

> Figure C-4 shows a schematic of the chip select circuit for the RAM.

> Figure C-4. Chip Select Circuit

> The current drain on the battery in a battery-backed circuit must be kept to a minimum. When the CPU card is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires +5 V to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control circuit accomplishes this task for the CS signal line.

> In a powered-up condition, the CS control circuit must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be battery voltage high). Q4 and Q5 are MOSFET transistors with opposing polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R31). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

> Transistors Q4 and Q5 are of opposite polarity so that a rail-to-rail voltage can be passed. When the /CS1 voltage is low, Q5 will conduct. When the /CS1 voltage is high, Q4 will conduct. It takes time for the transistors to turn on, creating a propagation delay. This delay is typically very small, about 10 ns to 15 ns.

> The signal that turns the transistors on is a high on the processor's reset line, /RES. When the CPU card is not in reset, the reset line will be high, turning on n-channel Q5. When a reset occurs, the /RES line will go low.

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