Smartcat (BL2100) User's Manual

> ## Appendix B. Power Supply

> Appendix B describes the power circuitry provided on the BL2100.

> ### B.1 Power Supplies

> Power is supplied to the BL2100 via pins 1 and 2 of screw-terminal header J4. The BL2100 is protected against reverse polarity by a diode at D1 as shown in Figure B-1.

> Figure B-1. BL2100 Power Supply

> The input voltage range is from 9 V to 36 V. A switching power regulator is used to provide a Vcc of +5 V for the BL2100 logic circuits. Vcc is not accessible to the user.

> The digital ground and the analog ground share a single split ground plane on the board, with the analog ground connected at a single point to the digital ground by a 0 W resistor (R29). This is done to minimize digital noise in the analog circuits and to eliminate the possibility of ground loops. External connections to analog ground are made on screw-terminal header J1, and external connections to digital ground are made on screw-terminal headers J4 and J11.

> #### B.1.1 Power for Analog Circuits

> Power to the analog circuits is provided by way of a two-stage low-pass filter, which isolates the analog section from digital noise generated by the other components. The analog power voltage +V powers the op-amp for the buffered A/D converter inputs, the A/D converter, the D/A converter, and the 4.096 V reference circuit. The maximum current draw on +V is less than 10 mA. +V is not accessible to the user.

> ### B.2 Batteries and External Battery Connections

> The SRAM and the real-time clock have battery backup. Power to the SRAM and the real-time clock (VRAM) is provided by two different sources, depending on whether the main part of the BL2100 is powered or not. When the BL2100 is powered normally, and Vcc is within operating limits, the SRAM and the real-time clock are powered from Vcc. If power to the board is lost or falls below 4.63 V, the VRAM and real-time clock power will come from the battery. The reset generator circuit controls the source of power by way of its /RESET output signal.

> A replaceable 265 mA·h lithium battery provides power to the real-time clock and SRAM when external power is removed from the circuit board. The drain on the battery is typically less than 10 µA when there is no external power applied to the BL2100, and so the expected shelf life of the battery is

> The drain on the battery is typically less than 4 µA when external power is applied, and so the expected BL2100 battery in-service life is

> A long-life 950 mA·h solder-in battery is also provided for in the board layout.

> #### B.2.1 Replacing the Backup Battery

> The battery is user-replaceable, and is fitted in a battery holder. To replace the battery, lift up on the spring clip and slide out the old battery. Use only a Panasonic CR2330 or equivalent replacement battery, and insert it into the battery holder with the + side facing up.

> NOTE | The SRAM contents and the real-time clock settings will be lost if the battery is replaced with no power applied to the BL2100. Excercise care if you replace the battery while external power is applied to the BL2100.
> NOTE | There is an explosion danger if the battery is short-circuited, recharged, or replaced incorrectly. Replace the battery only with the same type or an equivalent type recommended by the battery manufacturer. Dispose of used batteries according to the battery manufacturer's instructions.

> #### B.2.2 Battery-Backup Circuit

> Figure B-2 shows the battery-backup circuit located on the BL2100 module.

> Figure B-2. BL2100 Backup Battery Circuit

> The battery-backup circuit serves three purposes:

> - It reduces the battery voltage to the SRAM and to the real-time clock, thereby limiting the current consumed by the real-time clock and lengthening the battery life.
> - It ensures that current can flow only out of the battery to prevent charging the battery.
> - A voltage, VOSC, is supplied to U6, which keeps the 32.768 kHz oscillator working when the voltage begins to drop.

> VRAM and Vcc are nearly equal (<100 mV, typically 10 mV) when power is supplied to the BL2100.

> #### B.2.3 Power to VRAM Switch

> The VRAM switch on the BL2100 module, shown in Figure B-3, allows the battery backup to provide power when the external power goes off. The switch provides an isolation between Vcc and the battery when Vcc goes low. This prevents the Vcc line from draining the battery.

> Figure B-3. VRAM Switch

> Field-effect transistor Q5 is needed to provide a very small voltage drop between Vcc and VRAM (<100 mV, typically 10 mV) so that the board components powered by Vcc will not have a significantly different voltage than VRAM.

> When the BL2100 is not in reset, the /RESET line will be high. This turns on Q2, causing its collector to go low. This turns on Q5, allowing VRAM to nearly equal Vcc.

> When the BL2100 is in reset, the /RESET line will go low. This turns off Q2 and Q5, providing an isolation between Vcc and VRAM.

> #### B.2.4 Reset Generator

> The BL2100 module uses a reset generator on the module, U1, to reset the Rabbit 2000 microprocessor when the voltage drops below the voltage necessary for reliable operation. The reset occurs between 4.50 V and 4.75 V, typically 4.63 V.

> ### B.3 Chip Select Circuit

> Figure B-4 shows a schematic of the chip select circuit located on the BL2100 module.

> Figure B-4. Chip Select Circuit

> The current drain on the battery in a battery-backed circuit must be kept at a minimum. When the BL2100 is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control circuit accomplishes this task for the SRAM's chip select signal line.

> In a powered-up condition, the CS control circuit must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be battery voltage high). Q3 and Q4 are MOSFET transistors with complementary polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R28). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

> Transistors Q3 and Q4 are of opposite polarity so that a rail-to-rail voltage can be passed. When the /CS1 voltage is low, Q3 will conduct. When the /CS1 voltage is high, Q4 conducts. It takes time for the transistors to turn on, creating a propagation delay. This propagation delay is typically very small, about 10 ns to 15 ns.

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