Rabbit 3000 Microprocessor User's Manual

> ## 8. Memory Interface and Mapping

> ### 8.1 Interface for Static Memory Chips

> Static memory chips generally have address lines, data line, a chip select line, an output enable line and a write enable. The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips. The chip selects are not completely interchangeable because certain chip selects have special functions. When the processor starts up, not in cold boot mode, execution starts at address zero in the memory attached to /CS0. A static RAM should be connected to /CS1 because Dynamic C development tools assume a static RAM connected to /CS1.

> In addition /CS1 has special features that support battery backing of static RAM. When the processor power is removed but battery power is supplied to the battery power pin (VBAT) /CS1 is held in a high impedance state. This allows a pull up resistor to the battery backup power to hold /CS1 high and thus hold the static memory chip in standby mode. The RESOUT pin is also held high while the processor is powered down and battery power is supplied to VBAT. This allows the RESOUT pin to be used to control power to the processor and the static RAM chip via a transistor.

> It is also possible to force /CS1 to be enabled at all times. This is convenient if an external battery backup device is used that might slow down the transition of /CS1 during the memory cycle. Most users will not use this feature.

> Figure 8-1. Battery-Backup Circuit

> Figure 8-2. Typical Memory Chip Connection

> ### 8.2 Memory Mapping Overview

> See Section 3.2, "Memory Mapping," for a discussion of Rabbit memory mapping.

> Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips.

> Figure 8-3. Overview of Rabbit Memory Mapping

> ### 8.3 Memory-Mapping Unit

> The 64K 16-bit address space accessed by processor instructions is divided into segments. Each segment has a length that is a multiple of 4K. Except for the extended code segment, the segments have adjustable sizes and some segments can be reduced to zero size and thus vanish from the memory map.

> The four segments are shown in the example in Figure 8-4. The segment size register (SEGSIZE) determines the boundaries marked in the diagram. The extended code segment always occupies the addresses 0E000h-0FFFFh. The stack segment stretches from the address specified by the upper 4 bits of the SEGSIZE register to 0DFFFh. For example, if the upper 4 bits of SEGSIZE are 0Dh, then the stack segment will occupy 0D000h-0DFFFh, or 4K. If the upper 4 bits of SEGSIZE are greater than or equal to 0Eh, the stack segment vanishes. If these bits are set to zero, the two segments below the stack segment will vanish.

> The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure. If this boundary is equal to the upper boundary or greater than 0Eh, the data segment will vanish. If this segment is placed at zero the code segment will vanish.

> Figure 8-4. Memory Segments

> The memory management unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows.

> 1. It is determined which segment the 16-bit address belongs to by inspecting the upper 4 bits of the address. Every address must belong to one of the possible 4 segments.

> 2. Each segment has an 8-bit segment register. The 8-bit segment register is added to the upper 4 bits of the 16-bit address to create a 20-bit address. Wraparound occurs if the addition would result in an address that does not fit in 20 bits.

> Table 8-1. Segment Registers
> Segment Register | Function
> XPC | Locates extended code segment in physical memory. Read and written by processor instructions: ld a,xpc, ld xpc,a, lcall, lret, ljp
> STACKSEG = 11h | Locates stack segment in physical memory.
> DATASEG = 12h | Locates data segment in physical memory.

> Table 8-2. Segment Size Register
> | Bits 7..4 | Bits 3..0
> SEGSIZE = 13h | Boundary address stack segment. | Boundary address data segment.

> ### 8.4 Memory Interface Unit

> The 20-bit memory addresses generated by the memory-mapping unit feed into the memory interface unit. The memory interface unit has a separate write-only control register for each 256K quadrant of the 1M physical memory. This control register specifies how memory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit. There are three separate chip select output lines (/CS0, /CS1, and /CS2) that can be used to select one of three different memory chips. A field in the control register determines which chip select is selected for memory accesses to the quadrant. The same chip select line may be accessed in more than one quadrant. For example, if a 512K RAM is installed and is selected by /CS1, it would be appropriate to use /CS1 for accesses to the 3rd and 4th quadrants, thus mapping the RAM chip to addresses 80000h to 0FFFFFh.

> ### 8.5 Memory Bank Control Registers

> Table 8-3 describes the operation of the four memory bank control registers. The registers are write-only. Each register controls one quadrant in the 1M address space.

> Table 8-3. Memory Bank Control Register x (MBxCR=14h+x)
> Memory Bank x Control Register (MB0CR) (Address = 0x24) (MB1CR) (Address = 0x25) (MB2CR) (Address = 0x26) (MB3CR) (Address = 0x27)
> Bit(s) | Value | Description
> 7:6 | 00 | Four wait states for accesses in this bank.
> 01 | Two wait states for accesses in this bank.
> 10 | One wait states for accesses in this bank.
> 11 | Zero wait states for accesses in this bank.
> 5 | 0 | Pass A[19] for accesses in this bank.
> 1 | Invert A[19] for accesses in this bank.
> 4 | 0 | Pass A[18] for accesses in this bank.
> 1 | Invert A[18] for accesses in this bank.
> 3:2 | 00 | /OE0 and /WE0 are active for accesses in this bank
> 01 | /OE1 and /WE1 are active for accesses in this bank
> 10 | /OE0 only is active for accesses in this bank (i.e. read-only). Transactions are normal in every other way.
> 11 | /OE1 only is active for accesses in this bank (i.e. read-only). Transactions are normal in every other way.
> 1:0 | 00 | /CS0 is active for accesses in this bank.
> 01 | /CS1 is active for accesses in this bank.
> 1x | /CS2 is active for accesses in this bank.

> Bits 7,6--The number of wait states used in access to this quadrant. Without wait states, read requires 2 clocks and write requires 3 clocks. The wait state adds to these numbers. Wait states should only be used for memory data accesses (RAM or data flash), not for memory from which instructions are executed (code memory).

> Bits 5, 4--These bits allow the upper address lines to be inverted. This inversion occurs after the logic that selects the bank register, so setting these lines has no effect on which bank register is used. The inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip. The larger memory can then be accessed as 4 pages of 256K each. There is no effect outside the quadrant that the memory bank control register is controlling.

> Bit 3--Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash memory from an inadvertent write pulse, which will not actually write to the flash because it is protected by lock codes, but will temporarily disable the flash memory and crash the system if the memory is used for code.

> Bit 2--Selects which set of the two lines /OEx and /WEx will be driven for memory accesses in this quadrant.

> Bits 1,0--Determines which of the three chip select lines will be driven for memory accesses to this quadrant.

> All bits of the control register are initialized to zero on reset.

> ### 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable)

> The inversion of A19 or A16 controlled by the read/write MMIDR register is used to redirect mapping of the root segment and the data segment by inverting certain bits when these segments are accessed. Currently there is no planned use for this functionality.

> The optional enable of /CS1 is valuable for systems that are pushing the access time of battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1 high when power is off can be bypassed. This feature increases power consumption since the RAM is always enabled and its access is controlled normally by /OE1.

> Table 8-4. MMU Instruction/Data Register (MMIDR =010h)
> MMU Instruction/Data Register (MMIDR) (Address = 0x10)
> Bit(s) | Value | Description
> 7 | 0 | Normal timing for /OE1 (rising edge to rising edge, one clock minimum).
> 1 | Extended timing for /OE1 (one-half clock earlier than normal).
> 6 | 0 | Normal timing for /OE0.
> 1 | Extended timing for /OE0.
> 5 | 0 | Enable A16 and A19 inversion independent of instruction/data.
> 1 | Enable A16 and A19 inversion (controlled by bits 0-3) for data accesses only. This enables the instruction/data split. This bit is not present in the Rabbit 2000. This is separate I and D space.
> 4 | 0 | Normal /CS1 operation.
> 1 | Force /CS1 always active. This will not cause any conflicts as long as the memory using /CS1 does not also share an Output Enable or Write Enable with another memory.
> 3 | 0 | Normal operation.
> 1 | For a DATASEG access, invert A19 before MBxCR (bank select) decision.
> 2 | 0 | Normal operation.
> 1 | For a DATASEG access: invert A16
> 1 | 0 | Normal operation.
> 1 | For Root access, invert A19 before MBxCR (bank select) decision.
> 0 | 0 | Normal operation.
> 1 | For Root access: invert A16

> Table 8-5. MMU Expanded Code Register (MECR = 18h)
> MMU Expanded Code Register (MECR) (Address = 0x18)
> Bit(s) | Value | Description
> 7:3 |  | These bits are ignored for write, and return zeros when read.
> 2:0 | 0xx | Normal operation.
> 100 | For an XPC access, use MB0CR independent of A19-A18.
> 101 | For an XPC access, use MB1CR independent of A19-A18.
> 110 | For an XPC access, use MB2CR independent of A19-A18.
> 111 | For an XPC access, use MB3CR independent of A19-A18.

> ### 8.6 Allocation of Extended Code and Data

> The Dynamic C compiler compiles code to root code space or to extended code space. Root code starts in low memory and compiles upward.

> Allocation of extended code starts above the root code and data. Allocation normally continues to the end of the flash memory.

> Data variables are allocated to RAM working backwards in memory. Allocation normally starts at 52K in the 64K D space and continues. The 52K space must be shared with the root code and data, and is allocated upward from zero.

> Dynamic C also supports extended data constants. These are mixed in with the extended code in flash.

> ### 8.7 Instruction and Data Space Support

> Instruction and Data space (I and D space) support is accomplished by optionally inverting address lines A16 and/or A19 when the processor accesses D space, but not inverting those lines when the processor accesses I space. The MMIDR register (see Table 8-6) is used to control this inversion. It is important to understand that the bit inversion of A16 and A19 associated with I and D space occurs before the upper 2 bits of the 20 bit address are used to determine the quadrant and thus the bank register that is going to control memory access. This contrasts with the optional address bit inversion of A19 and A18 controlled by the 4 memory bank control registers (see Table 8-3) which takes place after the quadrant has been computed.

> Table 8-6. MMU Instruction/Data Register (MMIDR=010h)
> Bits 7:5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> 000 | 1-force /CS1 always enabled | 1-Invert A19 for data accesses in data segment before quadrant selection | 1-Invert A16 for data accesses in data segment | 1-Invert A19 for data accesses in root segment before quadrant selection | 1-Invert A16 for data accesses in root segment.

> To make this clear we will provide an example. Suppose a 1 megabyte flash memory is controlled by /CS0, /WE0, and /OE0. Suppose this memory is accessed as part of the first quadrant and MB0CR is set up to enable /CS0 and /WE0 or /OE0 on accesses to this bank. Then if A18 and A19 are zero, the first 256k bytes of the flash memory will be visible in the first 256k bytes of the physical memory. If access is made to the 2nd quadrant the memory will not be selected unless MB1CR is mapped to the flash memory. However if A18 is inverted by setting bit 4 in MB0CR to a 1, then the second 256k bytes of the flash will be mapped into the first quadrant. A18 will have been inverted, but he quadrant does not change because this inversion occurs after the quadrant has been selected.

> The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is used to separate I and D space to different memory locations. The separation of I and D space can only occur for the first 2 memory zones in the64k space. For each zone, the root
> code segment and the data segment either or both of A19 and A16 can be inverted. the reasoning behind these choices is the following. A normal memory map places flash memory in the lower 512k of the physical memory space. RAM memory begins at 512k. By inverting A19 on D space accesses memory mapped to the lower 512k and held in flash will be switched to RAM for D accesses. By inverting A16, D accesses will be switched to an adjacent 64k page, which would normally still be in the lower 512k memory or flash. To see how this works consider that data is of 2 different types: constants stored in flash memory and variables which must be stored in RAM. Because there are 2 types of data it is desirable to divide the D space into 2 zones, one for constants and one for variables. As shown in Figure 8-5. In a combined I and D space model the root code segment holds both code and data constants in flash memory. The data segment holds data variables in RAM. In the separate I and D space model the root code segment and the data segment are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash. In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space. However, if for D space accesses A16 is inverted for the root segment and A19 is inverted for the data segment, then root segment data is mapped to the next 64k of flash and data segment data is mapped to a place in memory 512k higher in the RAM. This divides the data space into 2 separate segments for constants and variables. If the stack segment (which is still combined I and D space) and the extended code segment (also combined I and D space) occupy 12k at the top of the 64k space, then the remaining 52k is doubled into a 52k code space in flash and a 52k data space which may be split into 2 parts, one for constants and one for variables. The relative size of the 2 parts depends on the lower 4 bits of the SEGSIZE register which defines the 4k page boundary between the root segment and the data segment.

> Figure 8-5. Combined versus Separate I & D Space

> The use of physical memory that goes with this map is shown in Figure 8-6, "Use of Physical Memory Separate I & D Space Model," on page 112. In this figure "n" is the number of 4k pages devoted to D space constants. In the figure it is assumed that the lower 512k of memory is entirely composed of flash memory and the upper 512k is entirely RAM. This does not have to be the case. For example if a low cost 32k x 8 RAM is used and mapped to the 3rd quadrant using /CS1 the RAM memory will begin at 512k and be repeated 8 times in the 3rd quadrant from addresses 512k to 768k. Since the memory repeats it can be considered to start at any address and continue for 32k bytes. At least 4k byte of RAM is needed for the stack segment, so if a 32k byte RAM is used a maximum of 28k would be available for storing data variables. If more stack segments are needed the amount of data variable space would be corresponding reduced.

> Figure 8-6. Use of Physical Memory Separate I & D Space Model

> In Figure 8-6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds. Each of these arrows starts at a constant location in physical memory. This is important because the Dynamic C debugging monitor needs to keep a small number of constants and variable in data space and it needs to be able to access these regardless of the state of the user program. The Dynamic C debugger variables are kept at the top of the data segment starting at 52k and working down in memory. The user-program variables are allocated by the compiler starting just below the Dynamic C debugger data. The Dynamic C constants start at address zero. User constants are allocated stating at a low address just above the Dynamic C constants.

> ### 8.8 How the Compiler Compiles to Memory

> The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory.

> In any but the smallest programs, most of the code is compiled to extended memory. This code executes in the 8K window from E000 to FFFF. This 8K window uses paged access. Instructions that use 16-bit addressing can jump within the page and also outside of the page to the remainder of the 64K space. Special instructions, particularly long call, long jump and long return, are used to access code outside of the 8K window. When one of these transfer of control instructions is executed, both the address and the view through the 8K window or page are changed. This allows transfer to any instruction in the 1M memory space. The 8-bit XPC register controls which of the 256 4K pages the 8K window aligns with. The 16-bit PC controls the address of the instruction, usually in the region E000 to FFFF. The advantage of paged access is that most instructions continue to use 16-bit addressing. Only when an out-of-range transfer of control is made does a 20-bit transfer of control need to be made. The beauty of having a 4K minimum step in page alignment while the size of the page is 8K is that code can be compiled continuously without gaps caused by change of page. When the page is moved by 4K, the previous end of code is still visible in the window, provided that the midpoint of the page was crossed before moving the page alignment.

> As the compiler compiles code in the extended code window, it checks at opportune times to see if the code has passed the midpoint of the window or F000. When the code passes F000, the compiler slides the window down by 4K so that the code at F000+x becomes resident at E000+x. This results in the code being divided into segments that are typically 4K long, but which can very short or as long as 8K. Transfer of control can be accomplished within each segment by 16-bit addressing; 20-bit addressing is required between segments.

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