Rabbit 2000™ Microprocessor Designer's Handbook

> ## 12. Troubleshooting Tips for New Rabbit-Based Systems

> When a user designs a new microprocessor system around the Rabbit and carefully follows the Rabbit design conventions, it is possible that the system will not boot up when Dynamic C is connected to the programming connector. This can happen because of a design error or even because of a random hardware defect in the new system. A hardware procedure is available to make it easier to debug systematically in such a situation.

> A series of steps may be performed in order to diagnosis a problem that keeps Dynamic C from booting.

> ### 12.1 Initial Checks

> Perform the following checks with the /RESET (pin 37) line tied to ground.

> - With a voltmeter check for the +5 V or other operating voltage on pins 3,28,53,78,92 and 42. Check for ground on pins 2, 27, 39, 52, 77 and 89.
> - With an oscilloscope check the 32.768 kHz oscillator on XTALA2 (pin 41). Make sure that it is oscillating and that the frequency is correct.
> - With an oscilloscope check the main system oscillator by observing the signal CLK (pin 1). With the reset held high this signal should have a frequency one eighth of the main crystal or oscillator frequency.

> ### 12.2 Diagnostic Test #2

> This test goes through a series of steps repeatedly. The steps are:

> 1. Apply the reset for approximately 1/4 second and then release the reset.
> 2. In cold boot send the following sequence of triplet characters to serial port A via the programming connector.

>     80 0E 20   // sets status pin low
>     80 0E 30   // sets status pin high
>     80 0E 20   // sets status pin low again

> 1. Wait for approximately 1/4 second and then repeat starting at step #1.

> While the test is running, an oscilloscope can be used to observe the results. The scope can be triggered by the reset line going high. It should be possible to observe the data characters being transmitted on the RXA pin of the processor or the programming connector. The status pin can also be observed at the processor or programming connector. Each byte transmitted has 8 data bits preceded by a start bit which is low and followed by a stop bit which is high (viewed at the processor or programming connector). The data bits are high for 1 and low for 0.

> The cold boot mode and the triplets sent are described in Section 4.1 on page 20. Each triplet consists of a 2-byte address and a 1-byte data value. The data value is stored in the address specified. The uppermost bit of the 16-bit address is set to one to specify an internal I/O write. The remaining 15 bits specify the address. If the write is to memory then the uppermost bit must be zero and the write must be to the first 32k of the memory space. The user should see the 9 bytes transmitted at 2400 bps or 416 µs per bit. The status bit will initially toggle fairly rapidly during the transmission of the first triplet because the default setting of the status bit is to go low on the first byte of an opcode fetch. While the triplets are being read instructions are being executed from the small cold boot program within the microprocessor. The status line will go low after the first triplet has been read. It will go high after the second triplet is finished. It will return to low again after the 3rd triplet is transmitted. and stay that way until the sequence starts again.

> If this test fails to function it may be that the programming connector is connected improperly or the proper pull-up resistors are not installed on the SMODE lines. Other possibilities are that one of the oscillators is not working or is operating at the wrong frequency. The reset could be failing.

> ### 12.3 Diagnostic Test #3

> This test checks the functioning of the RAM connected to /CS1/OE1/WE1. The test applies the reset, then sends a series of triplets to set up the necessary control registers. Then it writes several instructions to RAM. Finally it begins executing instructions in RAM. These instructions disable the watchdog timer.

>     80 14 05      //set MB0CR to 1 to select RAM
>     80 09 51      //ready watchdog for disable
>     80 09 54      //disable watchdog timer

>     //sequence of triplets to write program below to memory
>     // starting at address zero.

>     00 01 21
>     00 02 01
>     00 03 00
>     00 04 06
>     00 05 10
>     00 06 7e
>     00 07 29
>     00 08 10
>     00 09 FC
>     00 0A C3
>     00 0B 00

>     80 24 80       //terminate bootstrap, start at address zero

>     ;test program
>        ld hl,1
>        ld b,16
>     loop:
>        ld a,(hl)
>        add hl,hl ; shift left
>        djnz loop ; 16 steps
>        jp 0      ; continue test

> If this test runs it will toggle the first 16 address lines. In addition, all of the data lines must be functioning or the program would not execute correctly.

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