Jackrabbit (BL1800 Series) User's Manual

> ## Appendix C. Power Management

> ### C.1 Power Supplies

> Power is supplied to the Jackrabbit board from an external source through either header J1 or header J4. J1 is a 3-pin straight header with a pitch of 0.1". Vin is on pin 2 between ground on pins 1 and 3. The symmetry allows for a 3-pin cable to be connected either way.

> The Jackrabbit board itself is protected against reverse polarity by a Shottky diode at D2 as shown in Figure C-1. The Shottky diode has a low forward voltage drop, 0.3 V, which keeps the minimum DCIN required to power the Jackrabbit lower than a normal silicon diode would allow.

> Figure C-1. Jackrabbit Power Supply Schematic

> The external power, +RAW, is provided to any daughterboard connected to the Jackrabbit via pin 38 of header J4. +RAW is not protected against reversed polarity, such as could happen if the cable was connected to header J1 offset by one pin. This absence of protection is intentional so as to provide the maximum possible voltage to any daughterboard connected to the Jackrabbit.

> Capacitor C1 provides surge current protection for the voltage regulator, and allows the external power supply to be located some distance away from the Jackrabbit board. A switching power supply or a linear power supply option is provided, depending on the Jackrabbit model.

> The linear voltage regulator is simply a fixed-voltage regulator with a ±5% voltage output tolerance as the temperature changes. The regulator has a small heat sink, which increases the maximum external input voltage. Higher external input voltages increase the voltage dropped by the regulator. The Vcc coming out of the regulator is always 5 V.

> The power necessarily dissipated by the regulator can be calculated if both the external input voltage and the current drawn by the Jackrabbit board and daughterboards connected to the Jackrabbit board are known. The current provided by the high-power output drivers does not have to be included if a separate power supply is connected to K so that power does not come from Vcc.

> The linear regulator maintains its output voltage to within ±5% as long as the heat sink is dissipating less than 2 W. The regulator will operate outside its specifications when the heat sink is dissipating 2 W to 3.3 W. Thermal shutdown turns the regulator off above 3.3 W. Figure C-2 shows the power operating curves.

> Figure C-2. 7805 Linear Regulator Power Operating Curve

> The Jackrabbit operating at 14.7 MHz with no loading at the outputs typically consumes 105 mA when the programming cable is connected, and 95 mA when the programming cable is not connected. This means that DCIN can safely be from 7.5 V to 25 V. An additional 50 mA is available for a daughterboard, but the voltage regulation would suffer slightly.

> The switching voltage regulator is used when there is a need for an additional range in the external input voltage or when lower power consumption is desired. The input voltage range is from 8 V to 40 V.

> Figure C-3 shows typical power operating curves for both the linear regulator (BL1810 and BL1820) and the switching regulator (BL1800) for a nonloaded Jackrabbit operating at 14.7 MHz with the programming cable connected.

> Figure C-3. Typical Jackrabbit Current Consumption

> ### C.2 Batteries and External Battery Connections

> The soldered-in 950 mA·h lithium coin cell provides power to the real-time clock and SRAM when external power is removed from the circuit. This allows the Jackrabbit to continue to keep track of time and preserves the SRAM memory contents.

> The drain on the battery is typically less than 20 µA when there is no external power applied. The battery can last more than 5 years:

> The drain on the battery is typically less than 4 µA when there external power is applied. The battery can last for its full shelf life:

> Since the shelf life of the battery is 10 years, the battery can last for its full shelf life when external power is applied to the Jackrabbit.

> Header J2, shown in Figure C-4, allows external access to the battery. This header makes it possible to connect an external 3 V power supply while replacing the soldered-in 3 V lithium coin-type battery. This allows the Jackrabbit SRAM and real-time clock to retain data while the battery is being replaced.

> Figure C-4. External Battery Connections at Header J2

> Alternatively, header J2 can be used to accommodate an external battery. In this case, be sure to cut out the soldered-in battery on the Jackrabbit to prevent discharging the external battery into a dead battery.

> #### C.2.1 Battery Backup Circuit

> Figure C-5 shows the Jackrabbit battery backup circuitry.

> Figure C-5. Jackrabbit Battery Backup Circuit

> Resistor R12, shown in Figure C-5, is typically not stuffed on the Jackrabbit board. VRAM and Vcc are equal when power is supplied to the Jackrabbit. R13 prevents any catastrophic failure of Q1 from allowing unlimited current to enter the soldered-in battery.

> Resistors R14 and R15 make up a voltage divider between the battery voltage and the temperature-compensation voltage at the anode of diode D80. This voltage divider biases the base of Q1 to about 2.6 V. VBE on Q1 is about 0.55 V. Therefore, VRAM is about 2.05 V.

> These voltages vary with temperature. VRAM varies the least because temperature-compensation diodes D80-D82 will offset the variation with temperature of Q1 VBE. R80-R82 may be stuffed instead of the corresponding D80-D82 to provide the optimum temperature compensation.

> Resistor R10 provides a minimum load to the regulator circuit.

> The battery-backup circuit serves two purposes:

> - It reduces the battery voltage to the real-time clock, thereby reducing the current consumed by the real-time clock and lengthening the battery life.
> - It ensures that current can flow only out of the battery to prevent charging the battery.

> #### C.2.2 Power to VRAM Switch

> The VRAM switch, shown in Figure C-6, allows the soldered-in battery to provide power when the external power goes off. The switch provides an isolation between Vcc and the battery when Vcc goes low. This prevents the Vcc line from draining the battery.

> Figure C-6. VRAM Switch

> Transistor Q23 is needed to provide a very small voltage drop between Vcc and VRAM (<100 mV, typically 10 mV) so that the processor lines powered by Vcc will not have a significantly different voltage than VRAM.

> When the Jackrabbit is not resetting (pin 2 on U21 is high), the /RES line will be high. This turns on Q24, causing its collector (pin 3) to go low. This turns on Q23, allowing VRAM to nearly equal Vcc.

> When the Jackrabbit is resetting, the /RES line will go low. This turns off Q23 and Q24, providing an isolation between Vcc and VRAM.

> The battery backup circuit keeps VRAM from dropping below 2 V.

> #### C.2.3 Reset Generator

> The Jackrabbit uses a reset generator, U21, to reset the Rabbit 2000 microprocessor when the voltage drops below the voltage necessary for reliable operation. The Jackrabbit does not have a reset output presented to the headers. The reset generator has a reset input that can be used to force the Jackrabbit to reset. This input is available on headers J3 and J5, and also on pads directly below header J5. The two pads allow a screwdriver to be used to short the pads, forcing a reset.

> ### C.3 Chip Select Circuit

> Figure C-7 shows a schematic of the chip select circuit.

> Figure C-7. Chip Select Circuit

> The current drain on the battery in a battery-backed circuit must be kept at a minimum. When the Jackrabbit board is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control circuit accomplishes this task for the CS signal line.

> In a powered-up condition, the CS control circuit must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be battery voltage high). Q20 and Q21 are MOSFET transistors with opposing polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R37). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

> Transistors Q20 and Q21 are of opposite polarity so that a rail-to-rail voltages can be passed. When the /CS1 voltage is low, Q20 will conduct. When the /CS1 voltage is high, Q21 will conduct. It takes time for the transistors to turn on, creating a propagation delay. This delay is typically very small, about 10 ns to 15ns.

> The signal that turns the transistors on is a high on the processor's reset line, /RES. When the Jackrabbit is not in reset, the reset line will be high, turning on N-channel Q20 and Q22. Q22 is a simple inverter needed to turn on Q21, an P-channel MOSFET. When a reset occurs, the /RES line will go low. This will cause C23 to discharge through R42 and R40. This small delay (about 160 µs) ensures that there is adequate time for the processor to write any last byte pending to the SRAM before the processor puts itself into a reset state. When coming out of reset, CS will be enabled very quickly because D20 conducts to charge capacitor C23.

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