Rabbit 3000 Microprocessor User's Manual

> ## 9. Parallel Ports

> The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below.

> - Port A--Shared with the slave port data interface and auxiliary I/O data bus.

> - Port B--Shared with control lines for slave port, auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B.

> - Port C--Shared with serial port data I/O.

> - Port D--4 bits shared with alternate I/O pins for Serial Ports A and B. 4 bits not shared. Port D can be configured as open drain outputs. Port D also contains output preload registers that can be clocked into the output registers under timer control for pulse generation.

> - Port E--All bits of Port E can be configured as I/O strobes. 4 bits of port E can be used as external interrupt inputs. One bit of port E is shared with the slave port chip select. Port E has output preload registers that can be clocked into the output registers under timer control for pulse generation.

> - Port F-- As outputs, Port F can be configured as open drain outputs. Alternatively, Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As inputs, Parallel Port F inputs can carry the inputs to the two channels of the quadrature decoders. Port F pins can also be configured to be used as clock pins for clocked Serial Ports C and D.

> - Port G--As outputs, Port G can be configured as open drain outputs. Port G inputs and outputs are also used for access to other serial peripherals on the chip such as those used for asynchronous or SDLC/HDLC communication.

> Note that Parallel Ports D-G behave in the same manner when used as digital I/O.

> ### 9.1 Parallel Port A

> Parallel Port A has a single read/write register:

> Table 9-1. Parallel Port A registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port A Data Register | PADR | 0x30 | R/W | xxxxxxxx
> Slave Port Control Register | SPCR | 0x24 | R/W | 0xx00000

> Table 9-2. Parallel Port A Data Register bit functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PADR (R/W) adr = 030h | PA7 | PA6 | PA5 | PA4 | PA3 | PA2 | PA1 | PA0

> This register should not be used if the slave port or auxiliary I/O bus is enabled.

> The slave port control register is used to control whether Parallel Port A is configured as slave databus, auxiliary I/O data bus, parallel Input or parallel output. To make the port an input, store 080h in the SPCR (slave port control register). To make the port an output, store 084h in SPCR. Parallel Port A is set up as an input port on reset.

> When the port is read, the value read reflects the voltages on the pins, "1" for high and "0" for low. This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage.

> ### 9.2 Parallel Port B

> Parallel Port B, has eight pins that can programmed individually to be inputs and outputs.

> After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low.

> Table 9-3. Parallel Port B registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port B Data Register | PBDR | 0x40 | R/W | 00xxxxxx
> Port B Data Direction Register | PBDDR | 0x47 | W | 11000000

> Table 9-4. Parallel Port B register bit functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PBDR (R/W) adr = 040h | PB7 | PB6 | PB5 | PB4 | PB3 | PB2 | PB1 | PB0
> PBDDR (W) adr = 04Fh | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out

> When the auxiliary I/O bus is enabled, Parallel Port B bits 2:7 provide 6 address lines, the least significant 6 lines of the 16 lines that define the full I/O space.

> When the slave port is enabled, parallel port lines PB2-PB7 are assigned to various slave port functions. However, it is still possible to read PB0-PB5 using the Port B data register even when lines PB2-PB7 are used for the slave port. It is also possible to read the signal driving PB6 and PB7 (this signal is on the signaling lines from the slave port logic).

> Regardless of whether the slave port is enabled, PB0 reflects the input of the pin unless Serial Port B has its internal clock enabled, which causes this line to be driven by the serial port clock. PB1 reflects the input of the pin unless Serial Port A has its internal clock enabled.

> - PBDR--Parallel Port B data register. Read/Write.

> - PBDDR--Parallel Port B data direction register. A "1" makes the corresponding pin an output. This register is write only.

> ### 9.3 Parallel Port C

> Parallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the voltage on the pin. Bits 0,2,4,6 return the value of the signal driving the output buffers. The signal driving the output buffers and the value of the output pin are normally the same. Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin. The bits set in the PCFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins.

> Table 9-5. Parallel Port C Registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port C Data Register | PCDR | 0x50 | R/W | x1x1x1x1
> Port C Function Register | PCFR | 0x55 | W | x0x0x0x0

> Table 9-6. Parallel Port C register bit functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PCDR (r) adr = 050h | PC7 in | Echo drive | PC5 in | Echo drive | PC3 in | Echo drive | PC1 in | Echo drive
> PCDR (w) adr = 050h | x | PC6 | x | PC4 | x | PC2 | x | PC0
> PCFR (w) adr = 055h | x | Drive TXA | x | Drive TXB | x | Drive TXC | x | Drive TXD

> Parallel Port C shares its pins with serial ports A-D. The parallel port inputs can be configured as serial port inputs while the dedicated outputs as serial port outputs.

> When serving as serial inputs, the data lines can still be read from the Parallel Port C data register. The parallel port outputs can be selected to be serial port outputs by setting the corresponding bit positions in the Port C Function register (PCFR). When a parallel port output pin is selected to be a serial port output, the value stored in the data register is ignored.

> On reset the active (even-numbered) function register bits are zeroed resulting in Port C to behave as an I/O port. Bit 6 of the Port C data register is zeroed while the remaining even numbered bits are set to 1.

> ### 9.4 Parallel Port D

> Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses. Port D bits 4 and 5 can be used as alternate bits for Serial Port B, and bits 6 and 7 can be used as alternate bits for Serial Port A. Alternate serial port bit assignments make it possible for the same serial port to connect to different communications lines that are not operating at the same time.

> On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port D are not initialized on reset.

> Table 9-7. Parallel Port D Registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port D Data Register | PDDR | 0x60 | R/W | xxxxxxxx
> Port D Control Register | PDCR | 0x64 | W | xx00xx00
> Port D Function Register | PDFR | 0x65 | W | xxxxxxxx
> Port D Drive Control Register | PDDCR | 0x66 | W | xxxxxxxx
> Port D Data Direction Register | PDDDR | 0x67 | W | 00000000
> Port D Bit 0 Register | PDB0R | 0x68 | W | xxxxxxxx
> Port D Bit 1 Register | PDB1R | 0x69 | W | xxxxxxxx
> Port D Bit 2 Register | PDB2R | 0x6A | W | xxxxxxxx
> Port D Bit 3 Register | PDB3R | 0x6B | W | xxxxxxxx
> Port D Bit 4 Register | PDB4R | 0x6C | W | xxxxxxxx
> Port D Bit 5 Register | PDB5R | 0x6D | W | xxxxxxxx
> Port D Bit 6 Register | PDB6R | 0x6E | W | xxxxxxxx
> Port D Bit 7 Register | PDB7R | 0x6F | W | xxxxxxxx

> Figure 9-1. Parallel Port D Block Diagram

> Table 9-8. Parallel Port D Register functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PDDR (R/W) adr = 060h | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0
> PDDCR (W) adr = 066h | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain
> PDFR (W) adr = 065h | x | alt TXA | x | alt TXB | x | x | x | x
> PDDDR (W) adr = 067h | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out
> PDB0R (W) adr = 068h | x | x | x | x | x | x | x | PD0
> PDB1R (W) adr = 069h | x | x | x | x | x | x | PD1 | x
> PDB2R (W) adr = 06Ah | x | x | x | x | x | PD2 | x | x
> PDB3R (W) adr = 06Bh | x | x | x | x | PD3 | x | x | x
> PDB4R (W) adr = 06Ch | x | x | x | PD4 | x | x | x | x
> PDB5R (W) adr = 06Dh | x | x | PD5 | x | x | x | x | x
> PDB6R (W) adr = 06Eh | x | PD6 | x | x | x | x | x | x
> PDB7R (W) adr = 06Fh | PD7 | x | x | x | x | x | x | x

> Table 9-9. Parallel Port D Control Register (adr = 064h)
> Bits 7, 6 | Bits 5, 4 | Bits 3, 2 | Bits 1, 0
> x,x | 00--clock upper nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2 | x,x | 00--clock lower nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2

> The following registers are described in Table 9-8 and in Table 9-9.

> - PDDR--Parallel Port D data register. Read/Write.

> - PDDDR--Parallel Port D data direction register. A "1" makes the corresponding pin an output. Write only.

> - PDDCR--Parallel Port D drive control register. A "1" makes the corresponding pin an open-drain output if that pin is set up for output. Write only.

> - PDFR--Parallel Port D function control register. This port may be used to make port positions 4 and 6 be serial port outputs. Write only.

> - PDBxR--These eight registers may be used to set outputs on individual port positions.

> - PDCR--Parallel Port D control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero.

> ### 9.5 Parallel Port E

> Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually programmed as inputs or outputs. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses.

> Figure 9-2. Parallel Port E Block Diagram

> Table 9-10. Parallel Port E Registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port E Data Register | PEDR | 0x70 | R/W | xxxxxxxx
> Port E Control Register | PECR | 0x74 | W | xx00xx00
> Port E Function Register | PEFR | 0x75 | W | 00000000
> Port E Data Direction Register | PEDDR | 0x77 | W | 00000000
> Port E Bit 0 Register | PEB0R | 0x78 | W | xxxxxxxx
> Port E Bit 1 Register | PEB1R | 0x79 | W | xxxxxxxx
> Port E Bit 2 Register | PEB2R | 0x7A | W | xxxxxxxx
> Port E Bit 3 Register | PEB3R | 0x7B | W | xxxxxxxx
> Port E Bit 4 Register | PEB4R | 0x7C | W | xxxxxxxx
> Port E Bit 5 Register | PEB5R | 0x7D | W | xxxxxxxx
> Port E Bit 6 Register | PEB6R | 0x7E | W | xxxxxxxx
> Port E Bit 7 Register | PEB7R | 0x7F | W | xxxxxxxx

> The following registers are described in Table 9-11 and in Table 9-12.

> - PEDR--Port E data register. Reads value at pins. Writes to port E preload register.

> - PEDDR--Port E data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset.

> - PEFR--Port E function register. Set bit to "1" to make corresponding output an I/O strobe. The nature of the I/O strobe is controlled by the I/O bank control registers (IBxCR). The data direction must be set to output for the I/O strobe to work.

> - PEBxR--These are individual registers to set individual output bits on or off.

> - PECR--Parallel Port E control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero.

> On reset, the data direction register and function register are zeroed, making all pins inputs, and disabling the alternate output functions. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with Port E are not initialized on reset.

> Table 9-11. Parallel Port E Register functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PEDR (R/W) adr = 070h | PE7 | PE6 | PE5 | PE4 | PE3 | PE2 | PE1 | PE0
> PEFR (W) adr = 075h | alt /I7 | alt /I6 | alt /I5 | alt /I4 | alt /I3 | alt /I2 | alt /I1 | alt /I0
> PEDDR (W) adr = 077h | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out
> PEB0R (W) adr = 078h | x | x | x | x | x | x | x | PE0
> PEB1R (W) adr = 079h | x | x | x | x | x | x | PE1 | x
> PEB2R (W) adr = 07Ah | x | x | x | x | x | PE2 | x | x
> PEB3R (W) adr = 07Bh | x | x | x | x | PE3 | x | x | x
> PEB4R (W) adr = 07Ch | x | x | x | PE4 | x | x | x | x
> PEB5R (W) adr = 07Dh | x | x | PE5 | x | x | x | x | x
> PEB6R (W) adr = 07Eh | x | PE6 | x | x | x | x | x | x
> PEB7R (W) adr = 07Fh | PE7 | x | x | x | x | x | x | x

> Table 9-12. Parallel Port E Control Register (adr = 074h)
> Bits 7, 6 | Bits 5, 4 | Bits 3, 2 | Bits 1, 0
> x,x | 00--clock upper nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2 | x,x | 00--clock lower nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2

> ### 9.6 Parallel Port F

> Parallel Port F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register. As outputs, the bits of the port are buffered, with the data written to the Port F Data Register transferred to the output pins on a selected timing edge. The outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing.

> These inputs and outputs are also used for access to other peripherals on the chip. As outputs, the Parallel Port F outputs can carry the four Pulse-Width Modulator outputs. As inputs, Parallel Port F inputs can carry the inputs to the quadrature decoders. When Serial Port C or Serial Port D is used in the clocked serial mode, two pins of Parallel Port F are used to carry the serial clock signals. When the internal clock is selected in these serial ports, the corresponding bit of Parallel Port F is set as an output.

> The following registers are described in Table 9-14 and in Table 9-15.

> Table 9-13. Parallel Port F Registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port F Data Register | PFDR | 0x38 | R/W | xxxxxxxx
> Port F Control Register | PFCR | 0x3C | W | xx00xx00
> Port F Function Register | PFFR | 0x3D | W | xxxxxxxx
> Port F Drive Control Register | PFDCR | 0x3E | W | xxxxxxxx
> Port F Data Direction Register | PFDDR | 0x3F | W | 00000000

> Table 9-14. Parallel Port F Register Functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PFDR (R/W) adr = 03Fh | PF7 | PF6 | PF5 | PF4 | PF3 | PF2 | PF1 | PF0
> PFDCR (W) adr = 03Eh | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain
> PFFR (W) adr = 03Dh | pwm[3] | pwm[2] | pwm[1] | pwm[0] | x | x | sclk_c | sclk_d
> PFDDR (W) adr = 03Fh | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out

> Table 9-15. Parallel Port F Control Register (adr = 03Ch)
> Bits 7, 6 | Bits 5, 4 | Bits 3, 2 | Bits 1, 0
> x,x | 00--clock upper nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2 | x,x | 00--clock lower nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2

> The following registers are described in Table 9-14 and in Table 9-15.

> - PFDR--Port F data register. Reads value at pins. Writes to port F preload register.

> - PFDDR--Port F data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset.

> - PFFR--Port F function register. Set bit to "1" to enable alternate output function. Bits 7-4 enable the PWM outputs and bits 1-0 enable synchronous serial ports C and D clock outputs for when the serial port is configured for internal clock generation.

> - PFCR--Parallel Port F control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero.

> On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port F are not initialized on reset.

> ### 9.7 Parallel Port G

> Parallel Port G is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port G Data Register. As outputs, the bits of the port are buffered, with the data written to the Port G Data Register transferred to the output pins on a selected timing edge. The outputs of Timer A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate select field to control this timing.

> These inputs and outputs are also used for access to other peripherals on the chip. As outputs, Port G can carry the data and clock outputs from Serial Ports E and F. As inputs, Port G can carry the data and clock inputs for these two serial ports.

> The following registers are described in Table 9-17 and in Table 9-18.

> Table 9-16. Parallel Port G Registers
> Register Name | Mnemonic | I/O address | R/W | Reset
> Port G Data Register | PGDR | 0x48 | R/W | xxxxxxxx
> Port G Control Register | PGCR | 0x4C | W | xx00xx00
> Port G Function Register | PGFR | 0x4D | W | xxxxxxxx
> Port G Drive Control Register | PGDCR | 0x4E | W | xxxxxxxx
> Port G Data Direction Register | PGDDR | 0x4F | W | 00000000

> Table 9-17. Parallel Port G Data Register Functions
> | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0
> PGDR (R/W) adr = 048h | PG7 | PG6 | PG5 | PG4 | PG3 | PG2 | PG1 | PG0
> PGDCR (W) adr = 04Eh | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain | out = open drain
> PGFR (W) adr = 04Dh | x | SOUT_E | RCLK_E | TCLK_E | x | SOUT_F | RCLK_F | TCLK_F
> PGDDR (W) adr = 04Fh | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out | dir = out

> Table 9-18. Parallel Port G Control Register (adr= 04Ch)
> Bits 7, 6 | Bits 5, 4 | Bits 3, 2 | Bits 1, 0
> x,x | 00--clock upper nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2 | x,x | 00--clock lower nibble on pclk/2 01--clock on timer A1 10--clock on timer B1 11--clock on timer B2

> The following registers are described in Table 9-17 and in Table 9-18.

> - PGDR--Port G data register. Reads value at pins. Writes to port G preload register.

> - PGDDR--Port G data direction register. Set to "1" to make corresponding pin an output. This register is zeroed on reset.

> - PGFR--Port G function register. Set bit to "1" to enable alternate output function. Bits 6 and 2 enable the asycnhronous or SDLC/HDLC serial ports E and F outputs. And bits 5-4 and 1-0 enable the SDLC/HDLC transmit and receive clock outputs for serial ports E and F.

> - PGCR--Parallel Port F control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4, and 5 are reset to zero.

> On reset, the data direction register is zeroed, making all pins inputs. In addition certain bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the output registers when loaded. All other registers associated with port G are not initialized on reset.

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