Rabbit 3000 Microprocessor User's Manual

> ## 7. Miscellaneous Functions

> ### 7.1 Rabbit Oscillators and Clocks

> The Rabbit 3000 usually requires two separate clocks. The main clock normally drives the processor core and most of the peripheral devices. The 32.768 kHz clock is normally used to drive the battery backable time-date clock. The 32.768 kHz clock is also used to support remote cold boot via Serial Port A, driving the 2400 baud communications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power. The 32.768 kHz clock can be left out of a system provided that its functions are not required.

> An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main processor oscillator (Figure 7-1 on page 74). For lowest power an external oscillator may be substituted for the built in oscillator circuit. There are limitations on how low the operating power can be due to the requirement that the oscillator and time-date clock share the same power pin, making it impossible to restrict current to the buffer amplifier. An oscillator implemented using the built in buffer accepts crystals up to a frequency of 26 MHz (first overtone crystals only). This frequency may be then doubled by the clock doubler. The component values shown in the figure for the oscillator circuits are subject to adjustment depending on the crystal used and the operating frequency.

> The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and lengthening clock cycles. The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies. This limits the peak energy of the harmonics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests. The spectrum spreader has two operating modes, normal spreading and strong spreading. The spreader can also be turned off.

> Figure 7-1. Clock Distribution

> Table 7-1. Global Control/Status Register (I/O adr = 00h)
> Global Control/Status Register (GCSR) (Address = 0x00)
> Bit(s) | Value | Description
> 7:6 (rd-only) | 00 | No Reset or Watchdog Timer time-out since the last read.
> 01 | The Watchdog Timer timed out. These bits are cleared by a read of this register.
> 10 | This bit combination is not possible.
> 11 | Reset occurred. These bits are cleared by a read of this register.
> 5 | 0 | No effect on the Periodic interrupt. This bit will always be read as zero.
> 1 | Force a Periodic interrupt to be pending.
> 4:2 | xxx | See table below for decode of this field.
> 1:0 | 00 | Periodic interrupts are disabled.
> 01 | Periodic interrupts use Interrupt Priority 1.
> 10 | Periodic interrupts use Interrupt Priority 2.
> 11 | Periodic interrupts use Interrupt Priority 3.

> Table 7-2. Clock Select Field of GCSR
> Clock Select Bits 4:2 GCSR | CPU Clock | Peripheral Clock | Main Oscillator | Power-Save CS if Enabled by GPSCR
> 000 | osc/8 | osc/8 | on | short CS option
> 001 | osc/8 | osc | on | short CS option
> 010 | osc | osc | on | none
> 011 | osc/2 | osc/2 | on | none
> 100 | 32 kHz or fraction | 32 kHz or fraction | on | self-timed option
> 101 | 32 kHz or fraction | 32 kHz or fraction | off | self-timed option
> 110 | osc/4 | osc/4 | on | short CS option
> 111 | osc/6 | osc/6 | on | short CS option

> ### 7.2 Clock Doubler

> The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock.

> Table 7-3. Global Clock Double Register (GCDR, adr = 0fh)
> Global Clock Double Register (GCDR) (Address = 0x0F)
> Bit(s) | Value | Description
> 7:4 | xxxx | Reserved
> 3:0 | 0000 | The clock doubler circuit is disabled.
> 0001 | 6 ns nominal low time (4-9) 55+ MHz processor clock speed
> 0010 | 7 ns nominal low time (4.2-10.5) 50-55 MHz
> 0011 | 8 ns nominal low time (4.8-12) 45-50 MHz
> 0100 | 9 ns nominal low time (6-13.5) 38-45 MHz
> 0101 | 10 ns nominal low time (6-15) 29-38 MHz
> 0110 | 11 ns nominal low time (6.6-16.5) 20-29 MHz
> 0111 | 12 ns nominal low time (7.2-18) less than 20 MHz
> 1000 | 13 ns nominal low time
> 1001 | 14 ns nominal low time
> 1010 | 15 ns nominal low time
> 1011 | 16 ns nominal low time
> 1100 | 17 ns nominal low time
> 1101 | 18 ns nominal low time
> 1110 | 19 ns nominal Low time.
> 1111 | 20 ns nominal Low time

> When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a supply voltage of 3.3 V and a temperature of 25°C. The doubled-clock low time increases by 20% when the voltage is reduced to 2.5 V, and increases by about 40% when the voltage is reduced further to 2.0 V. The values increase or decrease by 1% for each 5°C increase or decrease in temperature. The doubled clock is created by xor'ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the built-in oscillator can be as asymmetric as 52-48, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used. However, the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses and the early option memory output enable.

> The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock doubler is used this will cause an additional asymmetry between alternate clock cycles.

> Figure 7-2. Effect of Clock Doubler

> The power consumption is proportional to the clock frequency, and for this reason power can be reduced by slowing the clock when less computing activity is taking place. The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme.

> ### 7.3 Clock Spectrum Spreader

> When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz. For lower frequencies the strong spreading has a greater effect in reducing the peak spectral strength as shown in the figure below.

> Figure 7-3. Reduction in Peak Spectral Strength from Spectrum Spreader

> In the normal spectrum spreading mode, the maximum shortening of the clock cycle is 3 nanoseconds at 3.3 V and 25°C. In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4.5 ns. The reduction in peak spectral strength is roughly independent of the clock frequency. Special precautions must be followed in setting the GCM0R and GCM1R registers (see Section 15.2, "Using the Clock Spectrum Spreader").

> ### 7.4 Chip Select Options for Low Power

> Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The Rabbit 3000 has optionally enabled modifications to the chip select behavior that reduce this unnecessary power consumption when the Rabbit 3000 is running at reduced clock speed.

> When the processor clock is divided (by 4, 6, or 8) so as to run at a lower speed the short chip select option can be enabled. When short chip select is enabled the chip select delays turning on until the end of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is divided by 6 the memory read cycle with no wait states would normally be 12 undivided clocks long. With the short chip select the chip select is on for only 2/12 clocks for a memory duty cycle of 1/6. If wait states are added the duty cycle is reduced even more. For example if there is one wait state and the clock is divided by 6 then the memory bus cycle will be 18 undivided clocks long and the duty cycle will be 2/18=1/9 with the short chip select option enabled.

> When the 32.768 kHz clock is used as the main processor clock (sleepy mode) the memory duty cycle can be reduced by enabling a self-timed chip select mode. When the 32.768 kHz clock is used the clock period is approximately 32 microseconds and a normal memory read cycle without wait states will be approximately 64 microseconds. No more than a few hundred nanoseconds are needed to read the memory. The main oscillator is normally shut down when operating at 32 kHz and no faster clock is available to time out a short chip select cycle. To provide for a low memory duty cycle a chip select and memory read can take place under control of a delay timer that is on the chip. The cycle starts at the start of the final 64 microsecond clock of the memory cycle and can be set to enable chip select for a period in the range of 70 to 200 nanoseconds. The data is clocked in early at the end of the delay driven cycle. The chip select duty cycle is very small, about 0.2/128=1/600.

> When operating in 32 kHz mode it is also possible to further divide the clock to a frequency as low as 2 kHz, further reducing execution speed and current consumption.

> Global Power Save Control Register (GPSCR) (Address = 0x0D)
> Bit(s) | Value | Description
> 7:5 | 000 | Self-timed chip selects are disabled.
> 001 | This bit combination is reserved and should not be used.
> 01x | This bit combination is reserved and should not be used.
> 100 | 296nS self-timed chip selects (192nS best case, 457nS worst case).
> 101 | 234nS self-timed chip selects (151nS best case, 360nS worst case).
> 110 | 171nS self-timed chip selects (111nS best case, 264nS worst case).
> 111 | 109nS self-timed chip selects (71nS best case, 168nS worst case).
> 4 | 0 | Normal Chip Select operation.
> 1 | Short Chip Select timing when dividing main oscillator by 4, 6, or 8.
> 3 | x | This bit is reserved and should not be used.
> 2:0 | 000 | The 32KHz clock divider is disabled.
> 001 | This bit combination is reserved and should not be used.
> 01x | This bit combination is reserved and should not be used.
> 100 | 32KHz oscillator divided by two (16.384KHz).
> 101 | 32KHz oscillator divided by four (8.192KHz).
> 110 | 32KHz oscillator divided by eight (4.096KHz).
> 111 | 32KHz oscillator divided by sixteen (2.048KHz).

> It is anticipated that these measures would reduce operating current consumption to as low as 20 µA plus some additional leakage that would be significant at high operating temperatures.

> Figure 7-4. Short Chip Select Memory Read

> Figure 7-5. Self-Timed Chip Select Memory Read Cycle

> ### 7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN

> Certain output pins can have alternate assignments as specified in Table 7-4.

> Table 7-4. Global Output Control Register (GOCR = 0Eh)
> Bit(s) | Value | Description
> 7:6 | 00 | CLK pin is driven with peripheral clock.
> 01 | CLK pin is driven with peripheral clock divided by 2.
> 10 | CLK pin is low.
> 11 | CLK pin is high.
> 5:4 | 00 | STATUS pin is active (low) during a first opcode byte fetch.
> 01 | STATUS pin is active (low) during an interrupt acknowledge.
> 10 | STATUS pin is low.
> 11 | STATUS pin is high.
> 3 | 1 | WDTOUTB pin is low (1 cycle minimum, 2 cycles maximum, of 32 kHz).
> 0 | WDTOUTB pin follows watchdog function.
> 2 | x | This bit is ignored.
> 1:0 | 00 | /BUFEN pin is active (low) during external I/O cycles.
> 01 | /BUFEN pin is active (low) during data memory accesses.
> 10 | /BUFEN pin is low.
> 11 | /BUFEN pin is high.

> ### 7.6 Time/Date Clock (Real-Time Clock)

> The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time for this ripple to take place is a few nanoseconds per bit, and certainly should not should not exceed 200 ns for all 8 bits, even when operating at low voltage.

> The 48 bits are enough bits to count up 272 years at the 32 kHz clock frequency. By convention, 12 AM on January 1, 1980, is taken as time zero. Z-World software ignores the highest order bit, giving the counter a capacity of 136 years from January 1, 1980. To read the counter value, the value is first transferred to a 6-byte holding register. Then the individual bytes may be read from the holding registers. To perform the transfer, any data bits are written to RTC0R, the first holding register. The counter may then be read as six 8-bit bytes at RTC0R through RTC5R. The counter and the 32 kHz oscillator are powered from a separate power pin that can be provided with power while the remainder of the chip is powered down. This design makes battery backup possible. Since the processor operates on a different clock than the RTC, there is the possibility of performing a transfer to the holding registers while a carry is taking place, resulting in incorrect information. In order to prevent this, the processor should do the clock read twice and make sure that the value is the same in both reads.

> If the processor is itself operating at 32 kHz, the read-clock procedure must be modified since a number of clock counts would take place in the time needed by the slow-clocked processor to read the clock. An appropriate modification would be to ignore the lower bytes and only read the upper 5 bytes, which are counted once every 256 clocks or every 1/128th of a second. If the read cannot be performed in this time, further low-order bits can be ignored.

> The RTC registers cannot be set by a write operation, but they can be cleared and counted individually, or by subset. In this manner, any register or the entire 48-bit counter can be set to any value with no more than 256 steps. If the 32 kHz crystal is not installed and the input pin is grounded, no counting will take place and the six registers can be used as a small battery-backed memory. Normally this would not be very productive since the circuitry needed to provide the power switchover could also be used to battery-back a regular low-power static RAM.

> Table 7-5. Real-Time Clock RTCxR Data Registers
> Real-Time Clock x Holding Register (RTC0R) R/W (Address = 0x02) (RTC1R) (Address = 0x03) (RTC2R) (Address = 0x04) (RTC3R) (Address = 0x05) (RTC4R) (Address = 0x06) (RTC5R) (Address = 0x07)
> Bit(s) | Value | Description
> 7:0 | Read | The current value of the 48-bit RTC holding register is returned.
> | Write | Writing to the RTC0R transfers the current count of the RTC to six holding registers while the RTC continues counting.

> Table 7-6. Real-Time Clock Control Register (RTCCR adr = 01h)
> Bit(s) | Value | Description
> 7:0 | 00h | No effect on the RTC counter, disable the byte increment function, or cancel the RTC reset command (except code 80h)
> 40h | Arm RTC for a reset with code 80h or reset and byte increment function with code 0c0h.
> 80h | Resets all six bytes of the RTC counter to 00h if proceeded by arm command 40h.
> c0h | Resets all six bytes of the RTC counter to 00h and enters byte increment mode--precede this command with 40h arm command.
> 7:6 | 01 | This bit combination must be used with every byte increment write to increment clock(s) register corresponding to bit(s) set to "1". Example: 01001101 increments registers: 0, 2,3. The byte increment mode must be enabled. Storing 00h cancels the byte increment mode.
> 5:0 | 0 | No effect on the RTC counter.
> 1 | Increment the corresponding byte of the RTC counter.

> ### 7.7 Watchdog Timer

> The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it "times out." When it times out, it emits a 1-clock pulse from the watchdog output pin and it resets the processor via an internal circuit. To prevent this timeout, the program must "hit" the watchdog timer before it times out. The hit is accomplished by storing a code in WDTCR.

> Table 7-7. Watchdog Timer Control Register (WDTCR adr = 08h)
> Bit(s) | Value | Description
> 7:0 | 5Ah | Restart (hit) the watchdog timer, with a 2-second timeout period.
> | 57h | Restart (hit) the watchdog timer, with a 1-second timeout period.
> | 59h | Restart (hit) the watchdog timer, with a 500 ms timeout period.
> | 53h | Restart (hit) the watchdog timer, with a 250 ms timeout period.
> | other | No effect on watchdog timer.

> The watchdog timer may be disabled by storing a special code in the WDTTR register. Normally this should not be done unless an external watchdog device is used. The purpose of the watchdog is to unhang the processor from an endless loop caused by a software crash or a hardware upset.

> It is important to use extreme care in writing software to hit the watchdog timer (or to turn off the watchdog timer). The programmer should not sprinkle instructions to hit the watchdog timer throughout his program because such instructions can become part of an endless loop if the program crashes and thus disable the recovery ability given by having a watchdog.

> The following is a suggested method for hitting the watchdog. An array of bytes is set up in RAM. Each of these bytes is a virtual watchdog. To hit a virtual watchdog, a number is stored in a byte. Every virtual watchdog is counted down by an interrupt routine driven by a periodic interrupt. This can happen every 10 ms. If none of the virtual watchdogs has counted down to zero, the interrupt routine hits the hardware watchdog. If any have counted down to zero, the interrupt routine disables interrupts, and then enters an endless loop waiting for the reset. Hits of the virtual watchdogs are placed in the user's program at "must exercise" locations.

> Table 7-8. Watchdog Timer Test Register (WDTTR adr = 09h)
> Bit(s) | Value | Description
> 7:0 | 51h | Clock the least significant byte of the WDT timer from the peripheral clock. (Intended for chip test and code 54h below only.)
> 52h | Clock the most significant byte of the WDT timer from the peripheral clock. (Intended for chip test and code 54h below only.)
> 53h | Clock both bytes of the WDT timer, in parallel, from the peripheral clock. (Intended for chip test and code 54h below only.)
> 54h | Disable the WDT timer. This value, by itself, does not disable the WDT timer. Only a sequence of two writes, where the first write is 51h, 52h or 53h, followed by a write of 54h, actually disables the WDT timer. The WDT timer will be re-enabled by any other write to this register.
> other | Normal clocking (32 kHz oscillator) for the WDT timer. This is the condition after reset.

> The code to do this may also hit the watchdog with a 0.25-second period to speed up the reset. Such watchdog code must be written so that it is highly unlikely that a crash will incorporate the code and continue to hit the watchdog in an endless loop. The following suggestions will help.

> 1. Place a jump to self before the entry point of the watchdog hitting routines. This prevents entry other than by a direct call or jump to the routine.

> 2. Before calling the routine, set a data byte to a special value and then check it in the routine to make sure the call came from the right caller. If not, go into an endless loop with interrupts disabled.

> 3. Maintain data corruption flags and/or checksums. If these go wrong, go into an endless loop with interrupts off.

> ### 7.8 System Reset

> The Rabbit 3000 contains a master reset input (pin 42), which initializes everything in the device except for the Real Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately. The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete, even if no write cycles were in progress at the start of the reset. Reset forces both the processor clock and the peripheral clock in the divide-by-eight mode. Note that if the processor is being clocked from the 32 kHz clock, the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in progress to be completed before the reset sequence completes and the clocks switch to divide-by-eight mode.

> During reset /CS1 is high impedance and all of the other memory and I/O control signals are held inactive (High). After the /RESET signal becomes inactive (High) the processor begins fetching instructions and the memory control signals begin normal operation. Note that the default values in the Memory Bank Control Registers select four wait states per access, so the initial program fetch memory reads are 48 clock cycles long (8 x (2 + 4)). Software can immediately adjust the processor timing to whatever the system requires.

> /CS1 is high-impedance during reset (and during power-down, when only VBAT is powered) to allow an external RAM connected to /CS1 to be powered by VBAT. This is possible because the /CS1 pin is powered by VBAT. In this case an external pull-up resistor (to VBAT) is required on /CS1 to keep the RAM deselected during power-down. If the external RAM connected to /CS1 is not powered by VBAT, so that any information held within it is lost during power-down, no pull-up resistor on MEMCS1B is appropriate, as this would add leakage (through the protection diode) to drain VBAT. The RESOUT signal, which is High during reset and power-down, can be used to control an external power switch to disconnect VDD from supplying VBAT.

> The default selection for the memory control signals consists of /CS0 and /OE0, and writes are disabled. This selection can also be immediately programmed to match the hardware configuration. A typical sequence would be to speed up the clock to full speed, followed by selection of the appropriate number of wait states and the chip select signals, output enable signals and write enable signals. At this point software would usually check the system status to determine what type of reset just occurred and begin normal operation.

> The default values for all of the peripheral control registers are shown with the following register listing. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros.

> ### 7.9 Rabbit Interrupt Structure

> An interrupt causes a call to be executed, pushing the PC on the stack and starting to execute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively. There are only two external interrupts generated by transitions on certain pins in Parallel Port E.

> The interrupt vectors are shown in Table 6-2.

> The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16-bit pointer to the routine. The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines.

> Interrupts have priority 1, 2 or 3. The processor operates at priority 0, 1, 2 or 3. If an interrupt is being requested, and its priority is higher than the priority of the processor, the interrupt will take place after then next instruction. The interrupt automatically raises the processor's priority to its own priority. The old processor priority is pushed into the 4-position stack of priorities contained in the IP register. Multiple devices can be requesting interrupts at the same time. In each case there is a latch set in the device that requests the interrupt. If that latch is cleared before the interrupt is latched by the central interrupt logic, then the interrupt request is lost and no interrupt takes place. This is shown in Table 7-9. The priorities shown in this table apply only for interrupts of the same priority level and are only meaningful if two interrupts are requested at the same time. Most of the devices can be programmed to interrupt at priority level 1, 2 or 3.

> Table 7-9. Interrupts--Priority and Action to Clear Requests
> Priority | Interrupt Source | Action Required to Clear the Interrupt
> Highest | External 1 | Automatically cleared by the interrupt acknowledge.
> | External 0 | Automatically cleared by the interrupt acknowledge.
> | Periodic (2 kHz) | Read the status from the GCSR.
> | Quadrature Decoder | Read the status from the QDSR.
> | Timer B | Read the status from the TBSR.
> | Timer A | Read the status from the TASR.
> | Input Capture | Read the status from the ICCSR.
> | Slave Port | Rd: Read the data from the SPD0R, SPD1R or SPD2R. Wr: Write data to the SPD0R, SPD1R, SPD2R or write a dummy byte to the SPSR.
> | Serial Port E | Rx: Read the data from the SEDR or SEAR. Tx: Write data to the SEDR, SEAR, SELR or write a dummy byte to the SESR.
> | Serial Port F | Rx: Read the data from the SFDR or SFAR. Tx: Write data to the SFDR, SFAR, SFLR or write a dummy byte to the SFSR.
> | Serial Port A | Rx: Read the data from the SADR or SAAR. Tx: Write data to the SADR, SAAR, SALR or write a dummy byte to the SASR.
> | Serial Port B | Rx: Read the data from the SBDR or SBAR. Tx: Write data to the SBDR, SBAR, SBLR or write a dummy byte to the SBSR.
> | Serial Port C | Rx: Read the data from the SCDR or SCAR. Tx: Write data to the SCDR, SCAR, SCLR or write a dummy byte to the SCSR.
> Lowest | Serial Port D | Rx: Read the data from the SDDR or SDAR Tx: Write date to the SDDR, SDAR, SDLR or write a dummy byte to the SDSR

> In the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take place, which automatically clears the request. A special action must be taken in the interrupt service routine for the other interrupts.

> ### 7.9.1 External Interrupts

> There are two external interrupts. Each interrupt has 2 input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either rising or falling edges.

> Figure 7-6. External Interrupt Line Logic

> The external interrupts take place on a transition of the input, which is programmable for rising, falling or both edges. The pulse catchers are programmable separately to detect a rising, falling, or either edge in the input. Each of the interrupt pins has its own catcher device to catch the edge transition and request the interrupt.

> When the interrupt takes place, both pulse catchers associated with that interrupt are automatically reset. If both edges are detected before the corresponding interrupt takes place, because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority, then there will be only one interrupt for the two edges detected. The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition, provided that the transitions are not too fast. Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit.

> Table 7-10. Control Registers for External Interrupts
> Reg Name | Reg Address | Bits 7,6 | Bits 5,4 | Bits 3,2 | Bits 1,0
> I0CR | 10011000 | xx | INT0B PE4 | INT0A PE0 | Enb INT0
> I1CR | 10011001 | xx | INT1B PE5 | INT1A PE1 | Enb INT1
> |  |  | edge triggered 00-disabled 10-rising 01-falling 11-both | edge triggered 00-disabled 10-rising 01-falling 11-both | interrupt 00-disable 01-pri 1 10-pri 2 11-pri 3

> ### 7.9.2 Interrupt Vectors: INT0 - EIR,00h/INT1 - EIR,08h

> When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt routines. Each additional interrupting device will have to signal the processor that it is requesting an interrupt. A separate signal line is needed for each device so that the processor can determine which devices are requesting an interrupt.

> The following code shows how the interrupt service routines can be written.

>     ; External interrupt Routine #0 (programmed priority could be 3)
>     int2:
>         push ip  ; save interrupt priority
>         ipset 1  ; set to priority really desired (1, 2, etc.)
>     ; insert body of interrupt routine here
>     ;
>         pop ip   ; get back entry priority
>         ipres    ; restore interrupted routine's priority
>         ret      ; return from interrupt

> ### 7.10 Bootstrap Operation

> The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0).

> Bootstrap operation inhibits the normal fetch of code from memory, and instead substitutes the output of a small internal boot ROM for program fetches. This bootstrap program reads groups of three bytes from the selected peripheral device. The first byte is the most significant byte of a 16-bit address, followed by the least-significant byte of a 16-bit address, followed by a byte of data. The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program. The most significant bit of the address is used to determine the destination for the byte of data. If this bit is zero, the byte is written to the memory location addressed by the downloaded address. If this bit is one, the byte is written to the internal peripheral addressed by the downloaded address. Note that all of the memory control signals continue to operate normally during bootstrap.

> Execution of the bootstrap program automatically waits for data to become available from the selected peripheral, and each byte transferred automatically resets the watchdog timer. However, the watchdog timer still operates, and bytes must be transferred often enough to prevent the watchdog timer from timing out.

> Bootstrap operation is terminated when the SMODE pins are set to zero. The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program. If the SMODE pins are zero, instructions are fetched from normal memory starting at address 0000h. The Slave Port Control register allows the bootstrap operation to be terminated remotely. Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately. So the sequence 80h, 24h and 80h will terminate bootstrap operation.

> Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address. So any time that the address ends in four zeros, if the SMODE pins are non-zero and bit 7 of the SPCR is zero, the bootstrap program will begin execution. This allows in-line downloading from the selected bootstrap port. Upon completion of the bootstrap operation, either by returning the SMODE pins to zero or setting the bit in the SPCR, execution will continue from where it was interrupted for the bootstrap operation.

> The Slave Port is selected for bootstrap operation when (SMODE1, SMODE0) = (0, 1). In this case the pins of Parallel Port A are used for a byte-wide data bus, and selected pins of Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data Register 0 is used for bootstrap operation, and any writes to the other data registers will be ignored by the processor, and can actually interfere with the bootstrap operation by masking the Write Empty signal.

> Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock. Note that the serial clock must be externally supplied for bootstrap operation. This precludes the use of a serial EEPROM for bootstrap operation.

> Serial Port A is selected for bootstrap operation as an asynchronous serial port when SMODE = 11. In this case bit 7 of Parallel Port C is used for the serial data and the 32 kHz oscillator is used to provide the serial clock. A dedicated divide circuit allows the use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous transfer. Only 2400 bps is supported for bootstrap operation, and the serial data must be eight bits for proper operation.

> When a bootstrap is performed using Serial Port A, the TXA signal is not needed since the bootstrap is a one-way communication. After the reset ends and the bootstrap mode begins, TXA will be low, reflecting its function as a parallel port output bit that is cleared by the reset. This may be interpreted as a break signal by some serial communication devices. TXA can be forced high by sending the triplet 80h, 50h, 40h, which stores 40h in Parallel Port C. An alternate approach is to send the triplet 80h, 55h, 40h, which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel Port C function register (55h).

> The transfer rate in any bootstrap operation must not be too fast for the processor to execute the instruction stream. The Write Empty signal acts as an interlock when using the Slave Port for bootstrap operation, because the next byte should not be written to the Slave Port until the Write Empty signal is active. No such interlock exists for the clocked serial and asynchronous bootstrap operation. In these cases, remember that the processor clock starts out in divide-by-eight mode with four wait states, and limit the transfer rate accordingly. In asynchronous mode at 2400 bps it takes about 4 ms to send each character, so no problem is likely unless the system clock is extremely slow.

> ### 7.11 Pulse Width Modulator

> The Pulse Width Modulator consists of a ten-bit free running counter, and four width registers. Each PWM output is High for "n+1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register. The PWM output High time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output. The PWM is clocked by the output of Timer A9.

> Register Name | Mnemonic | I/O address | R/W | Reset
> PWM LSB 0 Register | PWL0R | 0x88 | W | xxxxxxxx
> PWM MSB 0 Register | PWM0R | 0x89 | W | xxxxxxxx
> PWM LSB 1 Register | PWL1R | 0x8A | W | xxxxxxxx
> PWM MSB 1 Register | PWM1R | 0x8B | W | xxxxxxxx
> PWM LSB 2 Register | PWL2R | 0x8C | W | xxxxxxxx
> PWM MSB 2 Register | PWM2R | 0x8D | W | xxxxxxxx
> PWM LSB 3 Register | PWL3R | 0x8E | W | xxxxxxxx
> PWM MSB 3 Register | PWM3R | 0x8F | W | xxxxxxxx

> The spreading function is implemented by dividing each 1024-clock cycle into four quadrants of 256 clocks each. Within each quadrant, the Pulse Width Modulator uses the eight MSBs of each pulse-width register to select the base width in each of the quadrants. This is the equivalent to dividing the contents of the pulse-width register by four and using this value in each quadrant. To get the exact High time, the Pulse Width Modulator uses the two LSBs of the pulse-width register to modify the High time in each quadrant according to the table below. The "n/4" term is the base count, formed from the eight MSBs of the pulse-width register.

> Pulse Width LSBs | 1st | 2nd | 3rd | 4th
> 00 | n/4 + 1 | n/4 | n/4 | n/4
> 01 | n/4 + 1 | n/4 | n/4 + 1 | n/4
> 10 | n/4 + 1 | n/4 + 1 | n/4 + 1 | n/4
> 11 | n/4 + 1 | n/4 + 1 | n/4 + 1 | n/4 + 1

> The diagram below shows a PWM output for several different width values, for both modes of operation. Operation in the spread mode reduces the filtering requirements on the PWM output in most cases.

> ### 7.12 Input Capture

> The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt. The programmed conditions can also be used to start and stop the counter.

> Register Name | Mnemonic | I/O Address | R/W | Reset
> Input Capture Ctrl/Status Register | ICCSR | 0x56 | R/W | 00000000
> Input Capture Control Register | ICCR | 0x57 | W | xxxxxx00
> Input Capture Trigger 1 Register | ICT1R | 0x58 | W | 00000000
> Input Capture Source 1 Register | ICS1R | 0x59 | W | xxxxxxxx
> Input Capture LSB 1 Register | ICL1R | 0x5A | R | xxxxxxxx
> Input Capture MSB 1 Register | ICM1R | 0x5B | R | xxxxxxxx
> Input Capture Trigger 2 Register | ICT2R | 0x5C | W | 00000000
> Input Capture Source 2 Register | ICS2R | 0x5D | W | xxxxxxxx
> Input Capture LSB 2 Register | ICL2R | 0x5E | R | xxxxxxxx
> Input Capture MSB 2 Register | ICM2R | 0x5F | R | xxxxxxxx

> Because the Input Capture channels synchronize their inputs to the peripheral clock (further divided by Timer A8), there is some delay between the input transition and when an interrupt is requested, as shown below. The status bits in the ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR.

> Each Input Capture channel has two inputs, called the Start condition and the Stop condition. Each of these two inputs can be programmed to come from one of four bits (bits 1, 3, 5 or 7) in Parallel Port C, D, F or G. The two inputs can come from the same or different pins, and are edge-sensitive. Each input can be disabled, rising-edge-sensitive, falling-edge-sensitive or responsive to either edge polarity. Either or both inputs can generate an Input Capture interrupt, and either or both inputs can cause the current count to be latched.

> Each Input Capture counter operates in one of three modes, or can be disabled. The counter is never automatically reset, but must be reset by a software command. Although it does not generate an interrupt, there is a status bit which is set when the counter overflows (counts from FFFFh to 0000h) so that software can recognize this condition. To prevent potential stale-data problems, whenever the LSB of the latched count is read from the ICLxR, the corresponding MSB of the latched count is transferred to a holding register until read from the ICMxR.

> In the first mode the counter starts counting at the Start condition and stops counting at the Stop condition. This mode is useful for pulse width measurement if the Start condition and Stop condition are assigned to the same pin. The Input Capture inputs were chosen to take maximum advantage of this mode, to allow baud-rate detection for the serial ports and rotational speed measurement for the Quadrature Decoder channels. Using this mode with different inputs for the Start and Stop condition allows time-delay measurements between two signals. This is the mode to use for high-speed pulse measurement, because only one count latch is available, and it may be overwritten if the processor is not able to read the latched value quickly enough. When the counter starts from a known count only the stop count is necessary to determine the pulse width.

> In the second mode the counter runs continuously and the Start and Stop conditions merely latch the current count. This mode is useful for time-stamping the input conditions against the time reference of the counter. If the time-stamp feature is not needed, this mode gives the Rabbit 3000 up to four more external interrupt inputs. This mode works well for slower-speed pulse measurement, where the processor has enough time to read the count latched by the Start condition before the Stop condition occurs and latches a new count.

> In the third mode the counter runs continuously until the Stop condition occurs. This mode measures the time from the software-defined counter start until the Stop condition occurs on an input. Note that once the counter stops because of the Stop condition, it will not resume counting until re-enabled by software.

> ### 7.13 Quadrature Decoder

> The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an in-phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rotation and provide interrupts when the count goes from 00h to FFh or from FFh to 00h. The Quadrature Decoder contains digital filters on the inputs to prevent false counts. The Quadrature Decoder is clocked by the output of Timer A10.

> Register Name | Mnemonic | I/O Address | R/W | Reset
> Quad Decode Ctrl/Status Register | QDCSR | 0x90 | R/W | xxxxxxxx
> Quad Decode Control Register | QDCR | 0x91 | W | 00xx0000
> Quad Decode Count 1 Register | QDC1R | 0x94 | R | xxxxxxxx
> Quad Decode Count 2 Register | QDC2R | 0x96 | R | xxxxxxxx

> Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Port F. The I signal is input on an odd-numbered port bit, while the Q signal is input on an even-numbered port bit. There is also a disable selection, which is guaranteed not to generate a count increment or decrement on either entering or exiting the disable state. The operation of the counter as a function of the I and Q inputs is shown below.

> The Quadrature decoders are clocked by the output of Timer A10, giving a maximum clock rate of one-half of the peripheral clock rate. The time constant of Timer A10 must be fast enough to sample the inputs properly. Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock period wide. In addition, the clock rate must be High enough that transitions on the I and Q inputs are sampled in different clock cycles. The Input Capture may be used to measure the pulse width on the I inputs because they come from the odd-numbered port bits. The operation of the digital filter is shown below.

> The Quadrature Decoder generates an interrupt when the counter increments from FFh to 00h or when the counter decrements from 00h to FFh. The timing for the interrupt is shown below. Note that the status bits in the QDSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDSR.

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