MiniCom (OP6800) User's Manual

> ## Appendix B. Power Supply

> Appendix B describes the power circuitry provided on the OP6800.

> ### B.1 Power Supplies

> Power is supplied to the OP6800 via pins 20 and 21 of header J1, which is connected by a ribbon cable to either the Demonstration Board or to your system. The OP6800 is protected against reverse polarity by a diode at D6 as shown in Figure B-1.

> Figure B-1. OP6800 Power Supply

> The input voltage range is from 9 V to 36 V. A switching power regulator is used to provide a Vcc of +5 V for the OP6800 logic circuits. Vcc is not accessible to the user.

> NOTE | In addition to supplying +RAW to the OP6800 switching power regulator, the Demonstration Board has its own independent linear power regulator to supply the electronics in the demonstration area of the Demonstration Board. See Appendix C for more information.

> ### B.2 Batteries and External Battery Connections

> The SRAM and the real-time clock have provision for battery backup. Power to the SRAM and the real-time clock (VRAM) is provided by two different sources, depending on whether the main part of the OP6800 is powered or not. When the OP6800 is powered normally, and Vcc is within operating limits, the SRAM and the real-time clock are powered from Vcc. If power to the board is lost or falls below 4.63 V, the VRAM and real-time clock power must come from a backup battery in your system which you would connect to pin 40 of header J1 on the OP6800 via the ribbon cable. The backup battery should be able to supply 2.85 V-3.15 V at 10 µA.

> The reset generator circuit controls the source of power by way of its /RESET output signal.

> #### B.2.1 Battery-Backup Circuit

> Figure B-2 shows the battery-backup circuit located on the OP6800 module.

> Figure B-2. OP6800 Backup Battery Circuit

> The battery-backup circuit serves three purposes:

> - It reduces the battery voltage to the SRAM and to the real-time clock, thereby limiting the current consumed by the real-time clock and lengthening the battery life.
> - It ensures that current can flow only out of the battery to prevent charging the battery.
> - A voltage, VOSC, is supplied to U6, which keeps the 32.768 kHz oscillator working when the voltage begins to drop.

> VRAM and Vcc are nearly equal (<100 mV, typically 10 mV) when power is supplied to the OP6800.

> #### B.2.2 Power to VRAM Switch

> The VRAM switch on the OP6800 module, shown in Figure B-3, allows the battery backup to provide power when the external power goes off. The switch provides an isolation between Vcc and the battery when Vcc goes low. This prevents the Vcc line from draining the battery.

> Figure B-3. VRAM Switch

> Field-effect transistor Q5 is needed to provide a very small voltage drop between Vcc and VRAM (<100 mV, typically 10 mV) so that the board components powered by Vcc will not have a significantly different voltage than VRAM.

> When the OP6800 is not in reset, the /RESET line will be high. This turns on Q2, causing its collector to go low. This turns on Q5, allowing VRAM to nearly equal Vcc.

> When the OP6800 is in reset, the /RESET line will go low. This turns off Q2 and Q5, providing an isolation between Vcc and VRAM.

> #### B.2.3 Reset Generator

> The OP6800 module uses a reset generator on the module, U1, to reset the Rabbit 2000 microprocessor when the voltage drops below the voltage necessary for reliable operation. The reset occurs between 4.50 V and 4.75 V, typically 4.63 V.

> ### B.3 Chip Select Circuit

> Figure B-4 shows a schematic of the chip select circuit located on the OP6800 module.

> Figure B-4. Chip Select Circuit

> The current drain on the battery in a battery-backed circuit must be kept at a minimum. When the OP6800 is not powered, the battery keeps the SRAM memory contents and the real-time clock (RTC) going. The SRAM has a powerdown mode that greatly reduces power consumption. This powerdown mode is activated by raising the chip select (CS) signal line. Normally the SRAM requires Vcc to operate. However, only 2 V is required for data retention in powerdown mode. Thus, when power is removed from the circuit, the battery voltage needs to be provided to both the SRAM power pin and to the CS signal line. The CS control circuit accomplishes this task for the SRAM's chip select signal line.

> In a powered-up condition, the CS control circuit must allow the processor's chip select signal /CS1 to control the SRAM's CS signal /CSRAM. So, with power applied, /CSRAM must be the same signal as /CS1, and with power removed, /CSRAM must be held high (but only needs to be battery voltage high). Q3 and Q4 are MOSFET transistors with complementary polarity. They are both turned on when power is applied to the circuit. They allow the CS signal to pass from the processor to the SRAM so that the processor can periodically access the SRAM. When power is removed from the circuit, the transistors will turn off and isolate /CSRAM from the processor. The isolated /CSRAM line has a 100 kW pullup resistor to VRAM (R28). This pullup resistor keeps /CSRAM at the VRAM voltage level (which under no power condition is the backup battery's regulated voltage at a little more than 2 V).

> Transistors Q3 and Q4 are of opposite polarity so that a rail-to-rail voltage can be passed. When the /CS1 voltage is low, Q3 will conduct. When the /CS1 voltage is high, Q4 conducts. It takes time for the transistors to turn on, creating a propagation delay. This propagation delay is typically very small, about 10 ns to 15 ns.

Z-World http://www.zworld.com Voice: (530) 757-3737 FAX: (530) 757-3792 sales@zworld.com