/*****************************************************************************
* Copyright (c) 2007 Digi International Inc., All Rights Reserved
* 
* This software contains proprietary and confidential information of Digi
* International Inc.  By accepting transfer of this copy, Recipient agrees
* to retain this software in confidence, to prevent disclosure to others,
* and to make no use of this software other than that for which it was
* delivered.  This is an unpublished copyrighted work of Digi International
* Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
* prohibited.
* 
* Restricted Rights Legend
*
* Use, duplication, or disclosure by the Government is subject to
* restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
* Technical Data and Computer Software clause at DFARS 252.227-7031 or
* subparagraphs (c)(1) and (2) of the Commercial Computer Software -
* Restricted Rights at 48 CFR 52.227-19, as applicable.
*
* Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
*
*****************************************************************************/

#if !defined(iohub_reg_h)

#include "Npttypes.h"

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)


#ifdef __cplusplus
extern "C"
{
#endif


#define NA_IOHUB_ADDRESS_BASE                       (0x90000000)
#define NA_IOHUB_ADDRESS_INCREMENT                  (0x8000)

#define NA_IOHUB_IOP_0_INDEX                        (0)
#define NA_IOHUB_IOP_0_BASE_ADDRESS                 ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_IOP_0_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_IOP_1_INDEX                        (1)
#define NA_IOHUB_IOP_1_BASE_ADDRESS                 ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_IOP_1_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_UART_A_INDEX                       (2)
#define NA_IOHUB_UART_A_BASE_ADDRESS                ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_UART_A_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_UART_B_INDEX                       (3)
#define NA_IOHUB_UART_B_BASE_ADDRESS                ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_UART_B_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_UART_C_INDEX                       (4)
#define NA_IOHUB_UART_C_BASE_ADDRESS                ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_UART_C_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_UART_D_INDEX                       (5)
#define NA_IOHUB_UART_D_BASE_ADDRESS                ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_UART_D_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
/*
 * UART D and the A/D converter use the same DMA channel.
 */
#define NA_IOHUB_A2D_INDEX                          (5)
#define NA_IOHUB_A2D_BASE_ADDRESS                   ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_A2D_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))

#define NA_IOHUB_SPI_INDEX                          (6)
#define NA_IOHUB_SPI_BASE_ADDRESS                   ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_SPI_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
/* Note there is a gap in the register address space here */
#define NA_IOHUB_I2C_INDEX                          (10)
#define NA_IOHUB_I2C_BASE_ADDRESS                   ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_I2C_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
/* And here is another gap */
#define NA_IOHUB_FLEX_IO_0_INDEX                    (13)
#define NA_IOHUB_FLEX_IO_0_BASE_ADDRESS             ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_FLEX_IO_0_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))
#define NA_IOHUB_FLEX_IO_1_INDEX                    (14)
#define NA_IOHUB_FLEX_IO_1_BASE_ADDRESS             ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (NA_IOHUB_FLEX_IO_1_INDEX * NA_IOHUB_ADDRESS_INCREMENT)))


/*
 * Interrupt and FIFO Status register
 */
#define NA_IOHUB_IFS_INTERRUPT_PENDING          (1)
#define NA_IOHUB_IFS_INTERRUPT_NOT_PENDING      (0)

#define NA_IOHUB_IFS_PERIPHERAL_IDLE            (0)
#define NA_IOHUB_IFS_PERIPHERAL_BUSY            (1)




#define NA_IOHUB_IFS_rxncip                     31, 31
#define NA_IOHUB_IFS_rxecip                     30, 30
#define NA_IOHUB_IFS_rxnrip                     29, 29
#define NA_IOHUB_IFS_rxcaip                     28, 28
#define NA_IOHUB_IFS_rxpcip                     27, 27
#define NA_IOHUB_IFS_rxfofip                    26, 26
#define NA_IOHUB_IFS_rxfsrip                    25, 25
#define NA_IOHUB_IFS_txncip                     24, 24
#define NA_IOHUB_IFS_txecip                     23, 23
#define NA_IOHUB_IFS_txnrip                     22, 22
#define NA_IOHUB_IFS_txcaip                     21, 21
#define NA_IOHUB_IFS_txfufip                    20, 20
#define NA_IOHUB_IFS_txfsrip                    19, 19
#define NA_IOHUB_IFS_modip                      18, 18
#define NA_IOHUB_IFS_reserved1                  17, 16
#define NA_IOHUB_IFS_rxpbusy                    15, 15
#define NA_IOHUB_IFS_rx_fifo_full               14, 14
#define NA_IOHUB_IFS_rx_fifo_empty              13, 13
#define NA_IOHUB_IFS_txpbusy                    12, 12
#define NA_IOHUB_IFS_tx_fifo_full               11, 11
#define NA_IOHUB_IFS_tx_fifo_empty              10, 10
#define NA_IOHUB_IFS_reserved2                  9, 0

#define NA_IOHUB_IFS_RXNCIP_MASK                0x80000000
#define NA_IOHUB_IFS_RXECIP_MASK                0x40000000
#define NA_IOHUB_IFS_RXNRIP_MASK                0x20000000
#define NA_IOHUB_IFS_RXCAIP_MASK                0x10000000
#define NA_IOHUB_IFS_RXPCIP_MASK                0x08000000
#define NA_IOHUB_IFS_RXFOFIP_MASK               0x04000000
#define NA_IOHUB_IFS_RXFSRIP_MASK               0x02000000
#define NA_IOHUB_IFS_TXNCIP_MASK                0x01000000
#define NA_IOHUB_IFS_TXECIP_MASK                0x00800000
#define NA_IOHUB_IFS_TXNRIP_MASK                0x00400000
#define NA_IOHUB_IFS_TXCAIP_MASK                0x00200000
#define NA_IOHUB_IFS_TXFUFIP_MASK               0x00100000
#define NA_IOHUB_IFS_TXFSRIP_MASK               0x00080000
#define NA_IOHUB_IFS_MODIP_MASK                 0x00040000
#define NA_IOHUB_IFS_RXPBUSY_MASK               0x00008000
#define NA_IOHUB_IFS_RX_FIFO_FULL               0x00004000
#define NA_IOHUB_IFS_RX_FIFO_EMPTY              0x00002000
#define NA_IOHUB_IFS_TXPBUSY                    0x00001000
#define NA_IOHUB_IFS_TX_FIFO_FULL               0x00000800
#define NA_IOHUB_IFS_TX_FIFO_EMPTY              0x00000400

#define NA_IOHUB_IFS_getAddress(index)              ((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT)))



/*
 * Receive DMA control register
 */
#define NA_IOHUB_DMA_RX_CONTROL_CONTROLLED_BY_CPU       (0)
#define NA_IOHUB_DMA_RX_CONTROL_CONTROLLED_BY_FLEX_IO   (1)

#define NA_IOHUB_DMA_RX_CONTROL_DMA_MODE                (0)
#define NA_IOHUB_DMA_RX_CONTROL_DIRECT_ACCESS_MODE      (1)

#define NA_IOHUB_DMA_STATE_IDLE                         (0)

#define NA_IOHUB_DMA_RX_CONTROL_ce                  31, 31
#define NA_IOHUB_DMA_RX_CONTROL_ca                  30, 30
#define NA_IOHUB_DMA_RX_CONTROL_flex_io             29, 29
#define NA_IOHUB_DMA_RX_CONTROL_direct              28, 28
#define NA_IOHUB_DMA_RX_CONTROL_reserved1           27, 16
#define NA_IOHUB_DMA_RX_CONTROL_state               15, 10
#define NA_IOHUB_DMA_RX_CONTROL_index               9, 0


#define NA_IOHUB_DMA_RX_CONTROL_getAddress(index)   (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 1)




/*
 * Receive DMA Buffer Descriptor Pointer Register
 */
#define NA_IOHUB_DMA_RX_BDP_reg                     31, 0

#define NA_IOHUB_DMA_RX_BDP_getAddress(index)       (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 2)



/*
 * Receive DMA Interrupt Configuration Register
 */
#define NA_IOHUB_DMA_RX_ICR_ENABLED                 (1)
#define NA_IOHUB_DMA_RX_ICR_DISABLED                (0)

#define NA_IOHUB_DMA_RX_ICR_txthrs                  31, 29
#define NA_IOHUB_DMA_RX_ICR_reserved1               28, 27
#define NA_IOHUB_DMA_RX_ICR_rxfofie                 26, 26
#define NA_IOHUB_DMA_RX_ICR_rxfsrie                 25, 25
#define NA_IOHUB_DMA_RX_ICR_rxncie                  24, 24
#define NA_IOHUB_DMA_RX_ICR_rxecie                  23, 23
#define NA_IOHUB_DMA_RX_ICR_rxnrie                  22, 22
#define NA_IOHUB_DMA_RX_ICR_rxcaie                  21, 21
#define NA_IOHUB_DMA_RX_ICR_rxpcie                  20, 20
#define NA_IOHUB_DMA_RX_ICR_wstat                   19, 19
#define NA_IOHUB_DMA_RX_ICR_istat                   18, 18
#define NA_IOHUB_DMA_RX_ICR_lstat                   17, 17
#define NA_IOHUB_DMA_RX_ICR_fstat                   16, 16
#define NA_IOHUB_DMA_RX_ICR_blenstat                15, 0

#define NA_IOHUB_DMA_RX_ICR_getAddress(index)       (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 3)


/*
 * Direct Mode receive status FIFO
 */
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_reserved1    31, 14
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_empty        13, 13
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_full         12, 12
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_byte         11, 9
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_reserved2    8, 8
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_fflag        7, 7
#define NA_IOHUB_DIRECT_MODE_RX_STATUS_pstat        6, 0


#define NA_IOHUB_DIRECT_MODE_RX_STATUS_getAddress(index)    (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 4)



/*
 * Direct Mode receive data FIFO
 */
#define NA_IOHUB_DIRECT_MODE_RX_FIFO_reg            31, 0
#define NA_IOHUB_DIRECT_MODE_RX_FIFO_getAddress(index)      (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 5)


/*
 * Transmit DMA control register
 */
#define NA_IOHUB_DMA_TX_CONTROL_CONTROLLED_BY_CPU       (0)
#define NA_IOHUB_DMA_TX_CONTROL_CONTROLLED_BY_FLEX_IO   (1)

#define NA_IOHUB_DMA_TX_CONTROL_DMA_MODE                (0)
#define NA_IOHUB_DMA_TX_CONTROL_DIRECT_ACCESS_MODE      (1)


#define NA_IOHUB_DMA_TX_CONTROL_ce                  31, 31
#define NA_IOHUB_DMA_TX_CONTROL_ca                  30, 30
#define NA_IOHUB_DMA_TX_CONTROL_flex_io             29, 29
#define NA_IOHUB_DMA_TX_CONTROL_direct              28, 28
#define NA_IOHUB_DMA_TX_CONTROL_indexen             27, 26
#define NA_IOHUB_DMA_TX_CONTROL_reserved1           26, 16
#define NA_IOHUB_DMA_TX_CONTROL_state               15, 10
#define NA_IOHUB_DMA_TX_CONTROL_index               9, 0


#define NA_IOHUB_DMA_TX_CONTROL_getAddress(index)   (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 6)



/*
 * Transmit DMA Buffer Descriptor pointer register
 */
#define NA_IOHUB_DMA_TX_BDP_reg                     31, 0

#define NA_IOHUB_DMA_TX_BDP_getAddress(index)       (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 7)


/*
 * Transmit DMA interrupt configuration register
 */
#define NA_IOHUB_DMA_TX_ICR_txthrs                  31, 29
#define NA_IOHUB_DMA_TX_ICR_reserved1               28, 27
#define NA_IOHUB_DMA_TX_ICR_txfufie                 26, 26
#define NA_IOHUB_DMA_TX_ICR_txfsrie                 25, 25
#define NA_IOHUB_DMA_TX_ICR_txncie                  24, 24
#define NA_IOHUB_DMA_TX_ICR_txecie                  23, 23
#define NA_IOHUB_DMA_TX_ICR_txnrie                  22, 22
#define NA_IOHUB_DMA_TX_ICR_txcaie                  21, 21
#define NA_IOHUB_DMA_TX_ICR_reserved2               20, 20
#define NA_IOHUB_DMA_TX_ICR_wstat                   19, 19
#define NA_IOHUB_DMA_TX_ICR_istat                   18, 18
#define NA_IOHUB_DMA_TX_ICR_lstat                   17, 17
#define NA_IOHUB_DMA_TX_ICR_fstat                   16, 16
#define NA_IOHUB_DMA_TX_ICR_blenstat                15, 0


#define NA_IOHUB_DMA_TX_ICR_getAddress(index)       (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 8)




/*
 * Direct mode transmit data FIFO
 */
#define NA_IOHUB_DIRECT_MODE_TX_FIFO_reg       31, 0

#define NA_IOHUB_DIRECT_MODE_TX_FIFO_getAddress(index) (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 10)


/*
 * Direct mode transmit data last FIFO
 */
#define NA_IOHUB_DIRECT_MODE_TX_LAST_reg        31, 0

#define NA_IOHUB_DIRECT_MODE_TX_LAST_getAddress(index)  (((unsigned long volatile *)(NA_IOHUB_ADDRESS_BASE + (index * NA_IOHUB_ADDRESS_INCREMENT))) + 11)









#ifdef __cplusplus
}
#endif

#endif /* #if (PROCESSOR == ns9210) || (PROCESSOR == ns9215) */

#endif /* !defined(iohub_reg_h) */

