/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 * =======================================================================
 *  Module:
 *
 *      (SCM)           System Control Module
 *
 *  Register:
 *
 *
 *      (AAGCR)         AHB Aribiter Gen Configuration Register
 *      (BRC)           BRC Channel Register (0-15)
 *      (ABTPR)         AHB Bus (Aribter/Monitor) Timeout Register
 *      (AESR)          AHB Error Status Register (1-2)
 *      (AEMCR)         AHB Error Monitoring Configuration Register
 *      (TRCR)          Timer Reload Control Register (0-15)
 *      (TRR)           Timer Read Register (0-15)
 *      (IVAR)          Interrupt Vector Address Register (0-31)
 *      (ICR)           Interrupt Configuration Register (0-31)
 *      (ISRR)          Interrupt Service Routine Register
 *      (ISAR)          Interrupt Status Active Register
 *      (ISRAWR)        Interrupt Status Raw Register
 *      (SWCR)          Software Watch Dog Configuration Register
 *      (SWTR)          Software Watch Dog Timer  Register
 *      (CCR)           Clock Configuration Register
 *      (RSR)           Reset and Sleep Register
 *      (MSCSR)         Miscellanous System Configuration And Status Register        
 *      (PLL)           PLL Configuration Register
 *      (ILISR)         Interrupt Level Id Status Register
 *      (TCR)           Timer Control Register (0-15)
 *                                                                        
 * Edit Date/Ver   Edit Description
 * ==============  ===================================================
 * 
 *
 */

#ifndef SCM_REG_H
#define SCM_REG_H

#include "mcsys_reg.h"

#ifdef __cplusplus
extern "C"
{
#endif

/************************************************/
/* 	AHB Aribiter Gen Configuration Register     */
/************************************************/

/* Address Offset */
#define NA_SCM_AAGCR_ADDRESS    ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x000))

/* cpuMode */
#define SCM_AAGCR_DIRECT_EXT_MEM_ACCESS     0
#define SCM_AAGCR_ARBITRATE_MEM_ACCESS      1

/* AHB arbiter Gen Configuration register */
#define NA_SCM_AAGCR_REG_reserved_1		31, 1
#define NA_SCM_AAGCR_REG_cpuMode		0, 0
 

/************************************************/
/* BRC Channel Register (15-0)                  */
/************************************************/
/* Address  Offset  */
#define NA_SCM_BRCR0_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x004))
#define NA_SCM_BRCR1_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x008))
#define NA_SCM_BRCR2_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x00c))
#define NA_SCM_BRCR3_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x010))

#define SCM_BRCR_getAddress(index)  (NA_SCM_BRCR0_ADDRESS + (index/4))

/* enable */
#define SCM_BRCR_DISABLE            0
#define SCM_BRCR_ENABLE             1

/* bandwidth */
#define SCM_BRCR_100_PERCENT        0
#define SCM_BRCR_75_PERCENT         1
#define SCM_BRCR_50_PERCENT         2
#define SCM_BRCR_25_PERCENT         3

/* hmaster */
#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define NA_SCM_HMASTER_ARM926_ID                        0
#define NA_SCM_HMASTER_ETHERNET_RX                      1
#define NA_SCM_HMASTER_ETHERNET_TX                      2
#define NA_SCM_HMASTER_IO_HUB                           3
#define NA_SCM_HMASTER_EXTERNAL_DMA                     4

#define NA_SCM_HMASTER_COUNT                            5

#else

#define NA_SCM_HMASTER_ARM926_ID                        0
#define NA_SCM_HMASTER_ETHERNET_RX                      1
#define NA_SCM_HMASTER_ETHERNET_TX                      2
#define NA_SCM_HMASTER_JBIG                             3
#define NA_SCM_HMASTER_PCI                              4
#define NA_SCM_HMASTER_BBUS                             5
#define NA_SCM_HMASTER_LCD                              6    

#define NA_SCM_HMASTER_COUNT                            7
#endif

#define NA_SCM_BRCR_CHANNEL0_REG_enable         31, 31
#define NA_SCM_BRCR_CHANNEL0_REG_reserved_1     30, 30
#define NA_SCM_BRCR_CHANNEL0_REG_bandwidth      29, 28
#define NA_SCM_BRCR_CHANNEL0_REG_hmaster        27, 24

#define NA_SCM_BRCR_CHANNEL1_REG_enable         23, 23
#define NA_SCM_BRCR_CHANNEL1_REG_reserved_1     22, 22
#define NA_SCM_BRCR_CHANNEL1_REG_bandwidth      21, 20
#define NA_SCM_BRCR_CHANNEL1_REG_hmaster        19, 16

#define NA_SCM_BRCR_CHANNEL2_REG_enable         15, 15
#define NA_SCM_BRCR_CHANNEL2_REG_reserved_1     14, 14
#define NA_SCM_BRCR_CHANNEL2_REG_bandwidth      13, 12
#define NA_SCM_BRCR_CHANNEL2_REG_hmaster        11, 8

#define NA_SCM_BRCR_CHANNEL3_REG_enable         7, 7
#define NA_SCM_BRCR_CHANNEL3_REG_reserved_1     6, 6
#define NA_SCM_BRCR_CHANNEL3_REG_bandwidth      5, 4
#define NA_SCM_BRCR_CHANNEL3_REG_hmaster        3, 0

#define NA_SCM_BRCR_MAX_CHANNELS                16

/*
#define	  NA_SCM_BRCR0_CHANNEL0_REG;
#define   NA_SCM_BRCR0_CHANNEL1_REG;
#define   NA_SCM_BRCR0_CHANNEL2_REG;
#define   NA_SCM_BRCR0_CHANNEL3_REG;
#define   NA_SCM_BRCR1_CHANNEL4_REG;
#define   NA_SCM_BRCR1_CHANNEL5_REG;
#define   NA_SCM_BRCR1_CHANNEL6_REG;
#define   NA_SCM_BRCR1_CHANNEL7_REG;
#define   NA_SCM_BRCR2_CHANNEL8_REG;
#define   NA_SCM_BRCR2_CHANNEL9_REG;
#define   NA_SCM_BRCR2_CHANNEL10_REG;
#define   NA_SCM_BRCR2_CHANNEL11_REG;
#define   NA_SCM_BRCR3_CHANNEL12_REG;
#define   NA_SCM_BRCR3_CHANNEL13_REG;
#define   NA_SCM_BRCR3_CHANNEL14_REG;
#define   NA_SCM_BRCR3_CHANNEL15_REG;*/

/************************************************/
/*  AHB Bus (Aribter/Monitor) Timeout Register  */
/************************************************/

/* Address Offset */
#define NA_SCM_ABTPR_ADDRESS    ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x014))

#define NA_SCM_ABTPR_REG_arbiterTimeOut	31, 16
#define NA_SCM_ABTPR_REG_monitorTimeOut	15, 0
 

/************************************************/
/* AHB Error Status Register 1                  */ 
/************************************************/

/* Address Offset */
#define NA_SCM_AESR1_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x018))

#define NA_SCM_AESR1_REG_MC_BIT_TYPE_status 31, 0


/************************************************/
/* AHB Error Status Register 2                  */ 
/************************************************/

/* Address Offset */
#define NA_SCM_AESR2_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x01c))

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
#define NA_SCM_AESR2_REG_reserved_1		31, 20
#define NA_SCM_AESR2_REG_is_instruction_error   19,19
#define NA_SCM_AESR2_REG_is_data_error  18,18
#else
#define NA_SCM_AESR2_REG_reserved_1		31, 19
#define NA_SCM_AESR2_REG_burstLength	18, 18
#endif
#define NA_SCM_AESR2_REG_errorResponse	17, 17
#define NA_SCM_AESR2_REG_busMonitor		16, 16
#define NA_SCM_AESR2_REG_busArbiter		15, 15
#define NA_SCM_AESR2_REG_hwrite			14, 14
#define NA_SCM_AESR2_REG_hmaster		13, 10
#define NA_SCM_AESR2_REG_hport			9, 6
#define NA_SCM_AESR2_REG_hsize			5, 3
#define NA_SCM_AESR2_REG_hburst			2, 0


/************************************************/
/* AHB Error Monitoring Configuration Register  */
/************************************************/

/* Address Offset */
#define NA_SCM_AEMCR_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x020))

/* clearInterrupt */
/*      write 1 then 0 to clear     */

/* maxBurstIncrIgnore */
#define SCM_AEMCR_INCLUDE_INCR      0
#define SCM_AEMCR_IGNORE_INCR       1

/* maxBurstLengthDetect */
/* maxslaveErrorRespDetect */
/* busMonitorTimeout */
/* busArbiterTimeout */

#define SCM_AEMCR_RECORD_ERROR      0
#define SCM_AEMCR_GENERATE_IRQ      1
#define SCM_AEMCR_GENERATE_RESET    2
#define SCM_AEMCR_RESERVED          3

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
#define NA_SCM_AEMCR_REG_reserved_1                     31, 24
#define NA_SCM_AEMCR_REG_clearInterrupt                 23, 23
#define NA_SCM_AEMCR_REG_reserved_2                     22, 5
#define NA_SCM_AEMCR_REG_slaveErrorRespDetect           4, 4
#define NA_SCM_AEMCR_REG_busMonitorTimeout              3,0
#else
#define NA_SCM_AEMCR_REG_reserved_1                     31, 24
#define NA_SCM_AEMCR_REG_clearInterrupt                 23, 23
#define NA_SCM_AEMCR_REG_maxBurstIncrIgnore             22, 22
#define NA_SCM_AEMCR_REG_maxBurstLength                 21, 6
#define NA_SCM_AEMCR_REG_maxBurstLengthDetect           5, 5
#define NA_SCM_AEMCR_REG_slaveErrorRespDetect           4, 4
#define NA_SCM_AEMCR_REG_busMonitorTimeout              3, 2
#define NA_SCM_AEMCR_REG_busArbiterTimeout              1, 0
#endif

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/************************************************/
/*      Timer Master Control Register           */
/************************************************/

#define NA_SCM_TMCR_reserved1                           31, 22
#define NA_SCM_TMCR_timer9ReloadStepEnable              21, 21
#define NA_SCM_TMCR_timer9LowStepEnable                 20, 20
#define NA_SCM_TMCR_timer9HighStepEnable                19, 19
#define NA_SCM_TMCR_timer8ReloadStepEnable              18, 18
#define NA_SCM_TMCR_timer8LowStepEnable                 17, 17
#define NA_SCM_TMCR_timer8HighStepEnable                16, 16
#define NA_SCM_TMCR_timer7ReloadStepEnable              15, 15
#define NA_SCM_TMCR_timer7LowStepEnable                 14, 14
#define NA_SCM_TMCR_timer7HighStepEnable                13, 13
#define NA_SCM_TMCR_timer6ReloadStepEnable              12, 12
#define NA_SCM_TMCR_timer6LowStepEnable                 11, 11
#define NA_SCM_TMCR_timer6HighStepEnable                10, 10
#define NA_SCM_TMCR_timer9Enable                        9, 9
#define NA_SCM_TMCR_timer8Enable                        8, 8
#define NA_SCM_TMCR_timer7Enable                        7, 7
#define NA_SCM_TMCR_timer6Enable                        6, 6
#define NA_SCM_TMCR_timer5Enable                        5, 5
#define NA_SCM_TMCR_timer4Enable                        4, 4
#define NA_SCM_TMCR_timer3Enable                        3, 3
#define NA_SCM_TMCR_timer2Enable                        2, 2
#define NA_SCM_TMCR_timer1Enable                        1, 1
#define NA_SCM_TMCR_timer0Enable                        0, 0


#define NA_SCM_TMCR_ADDRESS             ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x024))

#endif


/************************************************/
/*      Timer Control Register                  */
/************************************************/
#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
    #define NA_SCM_TCR_MAX      10
#else
    #define NA_SCM_TCR_MAX      16
#endif

#if (PROCESSOR == ns9750) || (PROCESSOR == ns9360) || (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
    #define TCR_getAddress(index)(NA_SCM_TCR00_ADDRESS + index)
#endif

/*#define TCR_getRegister(index)(&TCR_registerTable[index])*/

/* Address Offset */
#define NA_SCM_TCR00_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x190))
#define NA_SCM_TCR01_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x194))
#define NA_SCM_TCR02_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x198))
#define NA_SCM_TCR03_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x19c))
#define NA_SCM_TCR04_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1a0))
#define NA_SCM_TCR05_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1a4))
#define NA_SCM_TCR06_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1a8))
#define NA_SCM_TCR07_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1ac))
#define NA_SCM_TCR08_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1b0))
#define NA_SCM_TCR09_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1b4))
#define NA_SCM_TCR10_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1b8))
#define NA_SCM_TCR11_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1bc))
#define NA_SCM_TCR12_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1c0))
#define NA_SCM_TCR13_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1c4))
#define NA_SCM_TCR14_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1c8))
#define NA_SCM_TCR15_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1cc))

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/* reloadMode */
#define SCM_TCR_USE_VALUE_IN_RELOAD_REGISTER        0
#define SCM_TCR_USE_HALF_VALUE_IN_RELOAD_REGISTER   1


/* timerMode2 */
#define SCR_TCR_USE_MODE1_VALUE     0
#define SCR_TCR_PWM_MODE            1
#define SCR_TCR_CLOCK_MODE          2
#define SCR_TCR_QUADRATURE          3
#endif

/* timerEnable */
#define SCM_TCR_DISABLE		        0
#define SCM_TCR_ENABLE		        1

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/* capComp   Capture and compare mode functions */
#define SCR_TCR_NORMAL                              0
#define SCR_TCR_COMPARE_AND_TOGGLE_OUTPUT           1
#define SCR_TCR_COMPARE_AND_PULSE_OUTPUT            2
#define SCR_TCR_CAPTURE_ON_FALLING_EDGE             3
#define SCR_TCR_CAPTURE_ON_RISING_EDGE              4
#define SCR_TCR_CAPTURE_ON_EVERY_2ND_RISING_EDGE    5
#define SCR_TCR_CAPTURE_ON_EVERY_4TH_RISING_EDGE    6
#define SCR_TCR_CAPTURE_ON_EVERY_8TH_RISING_EDGE    7

#endif


/* timer haltInDebugger */
#define SCM_TCR_RUN_IN_DEBUGGER     0
#define SCM_TCR_HALT_IN_DEBUGGER    1


/* timerClockSelect */
#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define SCM_TCR_AHB_CLOCK_TIMES_2   0
#define SCM_TCR_AHB_CLOCK           1
#define SCM_TCR_AHB_CLOCK_DIV_2     2
#define SCM_TCR_AHB_CLOCK_DIV_4     3
#define SCM_TCR_AHB_CLOCK_DIV_8     4
#define SCM_TCR_AHB_CLOCK_DIV_16    5
#define SCM_TCR_AHB_CLOCK_DIV_32    6
#define SCM_TCR_AHB_CLOCK_DIV_64    7
#define SCM_TCR_AHB_CLOCK_DIV_128   8
#define SCM_TCR_EXTERNAL_EVENT      15

#else

#define SCM_TCR_CPU_CLOCK           0
#define SCM_TCR_CPU_CLOCK_2         1
#define SCM_TCR_CPU_CLOCK_4         2
#define SCM_TCR_CPU_CLOCK_8         3
#define SCM_TCR_CPU_CLOCK_16        4
#define SCM_TCR_CPU_CLOCK_32        5
#define SCM_TCR_CPU_CLOCK_64        6
#define SCM_TCR_EXTERNAL_EVENT      7
#endif
/* timerMode */
#define SCM_TCR_INT_TIMER                       0
#define SCM_TCR_EXT_LOW_LEVEL_GATED_TIMER       1
#define SCM_TCR_EXT_HIGH_LEVEL_GATED_TIMER      2
#define SCM_TCR_CONCATENATE                     3

/* interruptSelect */
#define SCM_TCR_INTERRUPT_DISABLE               0
#define SCM_TCR_GENERATE_IRQ                    1

/* upDownSelect */
#define SCM_TCR_UP_COUNTER                      0
#define SCM_TCR_DOWN_COUNTER                    1

/* bitTimer */
#define SCM_TCR_16_BIT_TIMER                    0
#define SCM_TCR_32_BIT_TIMER                    1

/* reloadEnable */
#define SCM_TCR_HALT                            0
#define SCM_TCR_RESUME                          1

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/*
 * Note that besides the additional fields mode, some fields
 * have been shifted around.
 */
#define NA_SCM_TCR_REG_reloadMode               18, 18
#define NA_SCM_TCR_REG_mode2                    17, 16
#define NA_SCM_TCR_REG_enable                   15, 15
#define NA_SCM_TCR_REG_captureAndCompareMode    14, 12
#define NA_SCM_TCR_REG_haltInDebugger           11, 11
#define NA_SCM_TCR_REG_clearInterrupt           10, 10
#define NA_SCM_TCR_REG_clockSelect              9, 6
#define NA_SCM_TCR_REG_mode                     5, 4
#define NA_SCM_TCR_REG_interruptSelect          3, 3
#define NA_SCM_TCR_REG_upDownSelect             2, 2
#define NA_SCM_TCR_REG_bitTimer                 1, 1
#define NA_SCM_TCR_REG_reloadEnable             0, 0

#else

#define NA_SCM_TCR_REG_enable                   15, 15
#define NA_SCM_TCR_REG_reserved_1               14, 11
#define NA_SCM_TCR_REG_haltInDebugger           10, 10
#define NA_SCM_TCR_REG_clearInterrupt           9, 9
#define NA_SCM_TCR_REG_clockSelect              8, 6
#define NA_SCM_TCR_REG_mode                     5, 4
#define NA_SCM_TCR_REG_interruptSelect          3, 3
#define NA_SCM_TCR_REG_upDownSelect             2, 2
#define NA_SCM_TCR_REG_bitTimer                 1, 1
#define NA_SCM_TCR_REG_reloadEnable             0, 0

#endif
/*
typedef NA_SCM_TCR_TYPE * NA_SCM_TCR_TYPE_PTR;

#define NA_SCM_TCR00_REG    NA_SCM_TCR_REG   
#define NA_SCM_TCR01_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR02_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR03_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR04_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR05_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR06_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR07_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR08_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR09_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR10_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR11_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR12_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR13_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR14_REG    NA_SCM_TCR_REG
#define NA_SCM_TCR15_REG    NA_SCM_TCR_REG

extern  const NA_SCM_TCR_TYPE       NA_SCM_TCR_REG;
extern  const NA_SCM_TCR_TYPE_PTR   TCR_registerTable[16];*/

#if defined(NS9360) || defined(NS9750)
/************************************************/
/*      Timer Reload Count Register             */
/************************************************/

#define TRCR_getAddress(index)(NA_SCM_TRCR00_ADDRESS + index)
/*#define TRCR_getRegister(index)(TRCR_registerTable[index]);*/

#define NA_SCM_TRCR_MAX      16

/* Address Offset */
#define NA_SCM_TRCR00_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x044))
#define NA_SCM_TRCR01_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x048))
#define NA_SCM_TRCR02_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x04c))
#define NA_SCM_TRCR03_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x050))
#define NA_SCM_TRCR04_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x054))
#define NA_SCM_TRCR05_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x058))
#define NA_SCM_TRCR06_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x05c))
#define NA_SCM_TRCR07_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x060))
#define NA_SCM_TRCR08_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x064))
#define NA_SCM_TRCR09_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x068))
#define NA_SCM_TRCR10_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x06c))
#define NA_SCM_TRCR11_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x070))
#define NA_SCM_TRCR12_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x074))
#define NA_SCM_TRCR13_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x078))
#define NA_SCM_TRCR14_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x07c))
#define NA_SCM_TRCR15_ADDRESS                   ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x080))

#define NA_SCM_TRCR_REG_counter		31, 0
/*
#define NA_SCM_TRCR00_REG   NA_SCM_TRCR_REG
#define NA_SCM_TRCR01_REG   NA_SCM_TRCR_REG
#define NA_SCM_TRCR02_REG   NA_SCM_TRCR_REG
#define NA_SCM_TRCR03_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR04_REG   NA_SCM_TRCR_REG 
#define NA_SCM_TRCR05_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR06_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR07_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR08_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR09_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR10_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR11_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR12_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR13_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR14_REG   NA_SCM_TRCR_REG   
#define NA_SCM_TRCR15_REG   NA_SCM_TRCR_REG   

typedef NA_SCM_TRCR_TYPE * NA_SCM_TRCR_TYPE_PTR;

extern const NA_SCM_TRCR_TYPE       NA_SCM_TRCR_REG;
extern const NA_SCM_TRCR_TYPE_PTR   TRCR_registerTable[16]; */

/************************************************/
/*      Timer Read Register                     */
/************************************************/

#define TRR_getAddress(index)(NA_SCM_TRR00_ADDRESS + index)
#define TRR_getRegister(index)(TRR_registerTable[index])

#define NA_SCM_TRR_MAX      16

/* Address Offset */
#define NA_SCM_TRR00_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x084))
#define NA_SCM_TRR01_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x088))
#define NA_SCM_TRR02_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x08c))
#define NA_SCM_TRR03_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x090))
#define NA_SCM_TRR04_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x094))
#define NA_SCM_TRR05_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x098))
#define NA_SCM_TRR06_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x09c))
#define NA_SCM_TRR07_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0a0))
#define NA_SCM_TRR08_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0a4))
#define NA_SCM_TRR09_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0a8))
#define NA_SCM_TRR10_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0ac))
#define NA_SCM_TRR11_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0b0))
#define NA_SCM_TRR12_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0b4))
#define NA_SCM_TRR13_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0b8))
#define NA_SCM_TRR14_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0bc))
#define NA_SCM_TRR15_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0c0))

#define NA_SCM_TRR_REG_counter		31, 0
/*

#define NA_SCM_TRR00_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR01_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR02_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR03_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR04_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR05_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR06_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR07_REG    NA_SCM_TRR_REG 
#define NA_SCM_TRR08_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR09_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR10_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR11_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR12_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR13_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR14_REG    NA_SCM_TRR_REG
#define NA_SCM_TRR15_REG    NA_SCM_TRR_REG

extern const NA_SCM_TRR_TYPE        NA_SCM_TRR_REG;
extern const NA_SCM_TRR_TYPE_PTR    TRR_registerTable[16];*/


#elif (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/************************************************/
/*      Timer Reload and Compare register       */
/* When operating in 32-bit mode, the register  */
/* contains the 32-bit reload value.  If in     */
/* 16-bit mode, then bits 15-0 contain the      */
/* reload value, and bits 13-16 may contain     */
/* a compare value that causes an external      */
/* pulse to be generated when the value is      */
/* reached.                                     */
/************************************************/

#define TRCR_getAddress(index)(NA_SCM_TRCR00_ADDRESS + index)
/*#define TRCR_getRegister(index)(TRCR_registerTable[index]);*/

#define NA_SCM_TRCR_MAX      10


#define NA_SCM_TRCR00_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x028))
#define NA_SCM_TRCR01_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x02C))
#define NA_SCM_TRCR02_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x030))
#define NA_SCM_TRCR03_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x034))
#define NA_SCM_TRCR04_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x038))
#define NA_SCM_TRCR05_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x03C))
#define NA_SCM_TRCR06_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x040))
#define NA_SCM_TRCR07_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x044))
#define NA_SCM_TRCR08_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x048))
#define NA_SCM_TRCR09_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x04C))

#define NA_SCM_TRCR_REG_compareCount                31, 16
#define NA_SCM_TRCR_REG_counter                     31, 0
#define NA_SCM_TRCR_REG_counter16                   15, 0





/************************************************/
/*      Timer Read and Capture Register         */
/* When operating in 32-bit mode, the register  */
/* contains the 32-bit read value.  If in       */
/* 16-bit mode, then bits 15-0 contain the      */
/* read value, and bits 13-16 may contain a     */
/* capture value.                               */
/************************************************/

#define TRR_getAddress(index)              (NA_SCM_TRR00_ADDRESS + index)


#define NA_SCM_TRR00_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x050))
#define NA_SCM_TRR01_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x054))
#define NA_SCM_TRR02_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x058))
#define NA_SCM_TRR03_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x05C))
#define NA_SCM_TRR04_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x060))
#define NA_SCM_TRR05_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x064))
#define NA_SCM_TRR06_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x068))
#define NA_SCM_TRR07_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x06C))
#define NA_SCM_TRR08_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x070))
#define NA_SCM_TRR09_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x074))

#define NA_SCM_TRR_REG_captureRead             31, 16
#define NA_SCM_TRR_REG_counter                 31, 0
#define NA_SCM_TRR_REG_counter16               15, 0



/************************************************/
/*      Timer High Registers                    */
/* The value at which the PWM output is toggle  */
/* high.  Only timers 6-9 support this          */
/************************************************/

#define THIGH_getAddress(index)         (NA_ASSERT((index >=6) && (index <= 9)),  NA_SCM_THIGH6_ADDRESS + (index - 6))


#define NA_SCM_THIGH6_ADDRESS               ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x078))
#define NA_SCM_THIGH7_ADDRESS               ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x07C))
#define NA_SCM_THIGH8_ADDRESS               ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x080))
#define NA_SCM_THIGH9_ADDRESS               ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x084))



/************************************************/
/*      Timer Low Registers                     */
/* The value at which the PWM output is toggle  */
/* low.  Only timers 6-9 support this           */
/************************************************/

#define TLOW_getAddress(index)          (NA_ASSERT((index >=6) && (index <= 9)),  NA_SCM_TLOW6_ADDRESS + (index - 6))

#define NA_SCM_TLOW6_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x088))
#define NA_SCM_TLOW7_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x08C))
#define NA_SCM_TLOW8_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x090))
#define NA_SCM_TLOW9_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x094))

/************************************************/
/*      Timer High and Low Step Registers       */
/* These registers contain values that are      */
/* added or subtracted from the original high   */
/* and low register values each cycle.          */
/************************************************/

#define NA_SCM_THLS_SUBTRACT                    0
#define NA_SCM_THLS_ADD                         1

#define NA_SCM_THLS_highStepDirection           31, 31
#define NA_SCM_THLS_highStepValue               30, 16
#define NA_SCM_THLS_lowStepDirection            15, 15
#define NA_SCM_THLS_lowStepValue                14, 0

#define THLS_getAddress(index)          (NA_ASSERT((index >=6) && (index <= 9)),  NA_SCM_THLS6_ADDRESS + (index - 6))

#define NA_SCM_THLS6_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x098))
#define NA_SCM_THLS7_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x09C))
#define NA_SCM_THLS8_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0A0))
#define NA_SCM_THLS9_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0A4))

/************************************************/
/*      Timer Reload Step Registers             */
/* These registers contain values that are      */
/* added or subtracted from the original high   */
/* and low register values each cycle.          */
/************************************************/

#define NA_SCM_TRS_SUBTRACT                    0
#define NA_SCM_TRS_ADD                         1

#define NA_SCM_TRS_reserved                 31, 16
#define NA_SCM_TRS_stepDirection            15, 15
#define NA_SCM_TRS_stepValue                14, 0

#define TRS_getAddress(index)               (NA_ASSERT((index >=6) && (index <= 9)),  NA_SCM_TRS6_ADDRESS + (index - 6))

#define NA_SCM_TRS6_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0A8))
#define NA_SCM_TRS7_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0AC))
#define NA_SCM_TRS8_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0B0))
#define NA_SCM_TRS9_ADDRESS                ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x0B4))

#endif



/************************************************/
/*  Interrupt Vector Address Register (0-31)    */
/************************************************/

#define NA_SCM_IVAR_MAX     32

#define IVAR_getAddress(index)(NA_SCM_IVAR00_ADDRESS + index)

/* Address Offset */
#define NA_SCM_IVAR00_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0c4))
#define NA_SCM_IVAR01_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0c8))
#define NA_SCM_IVAR02_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0cc))
#define NA_SCM_IVAR03_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0d0))
#define NA_SCM_IVAR04_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0d4))
#define NA_SCM_IVAR05_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0d8))
#define NA_SCM_IVAR06_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0dc))
#define NA_SCM_IVAR07_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0e0))
#define NA_SCM_IVAR08_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0e4))
#define NA_SCM_IVAR09_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0e8))
#define NA_SCM_IVAR10_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0ec))
#define NA_SCM_IVAR11_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0f0))
#define NA_SCM_IVAR12_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0f4))
#define NA_SCM_IVAR13_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0f8))
#define NA_SCM_IVAR14_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x0fc))
#define NA_SCM_IVAR15_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x100))
#define NA_SCM_IVAR16_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x104))
#define NA_SCM_IVAR17_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x108))
#define NA_SCM_IVAR18_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x10c))
#define NA_SCM_IVAR19_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x110))
#define NA_SCM_IVAR20_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x114))
#define NA_SCM_IVAR21_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x118))
#define NA_SCM_IVAR22_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x11c))
#define NA_SCM_IVAR23_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x120))
#define NA_SCM_IVAR24_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x124))
#define NA_SCM_IVAR25_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x128))
#define NA_SCM_IVAR26_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x12c))
#define NA_SCM_IVAR27_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x130))
#define NA_SCM_IVAR28_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x134))
#define NA_SCM_IVAR29_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x138))
#define NA_SCM_IVAR30_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x13c))
#define NA_SCM_IVAR31_ADDRESS           ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x140))

#define NA_SCM_IVAR_REG_address		31, 0
 

/************************************************/
/*  Interrupt Configuration Register (0-31)     */
/************************************************/
#define NA_SCM_ICR_MAX      32

#define ICR_getAddress(index)(NA_SCM_ICR00_ADDRESS + (index/4))
/*#define ICR_getRegister(index)  NA_SCM_ICR ## (index%4) ##_REG*/

/* Address Offset */
/* Each Interrupt Config Register is 8 bits */
/* Register is 32 bit accessed */

#define NA_SCM_ICR00_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x144))
#define NA_SCM_ICR01_ADDRESS                NA_SCM_ICR00_ADDRESS
#define NA_SCM_ICR02_ADDRESS                NA_SCM_ICR00_ADDRESS
#define NA_SCM_ICR03_ADDRESS                NA_SCM_ICR00_ADDRESS

#define NA_SCM_ICR04_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x148))
#define NA_SCM_ICR05_ADDRESS                NA_SCM_ICR04_ADDRESS
#define NA_SCM_ICR06_ADDRESS                NA_SCM_ICR04_ADDRESS
#define NA_SCM_ICR07_ADDRESS                NA_SCM_ICR04_ADDRESS

#define NA_SCM_ICR08_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x14c))
#define NA_SCM_ICR09_ADDRESS                NA_SCM_ICR08_ADDRESS
#define NA_SCM_ICR10_ADDRESS                NA_SCM_ICR08_ADDRESS
#define NA_SCM_ICR11_ADDRESS                NA_SCM_ICR08_ADDRESS

#define NA_SCM_ICR12_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x150))
#define NA_SCM_ICR13_ADDRESS                NA_SCM_ICR12_ADDRESS
#define NA_SCM_ICR14_ADDRESS                NA_SCM_ICR12_ADDRESS
#define NA_SCM_ICR15_ADDRESS                NA_SCM_ICR12_ADDRESS

#define NA_SCM_ICR16_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x154))
#define NA_SCM_ICR17_ADDRESS                NA_SCM_ICR16_ADDRESS
#define NA_SCM_ICR18_ADDRESS                NA_SCM_ICR16_ADDRESS
#define NA_SCM_ICR19_ADDRESS                NA_SCM_ICR16_ADDRESS

#define NA_SCM_ICR20_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x158))
#define NA_SCM_ICR21_ADDRESS                NA_SCM_ICR20_ADDRESS
#define NA_SCM_ICR22_ADDRESS                NA_SCM_ICR20_ADDRESS
#define NA_SCM_ICR23_ADDRESS                NA_SCM_ICR20_ADDRESS

#define NA_SCM_ICR24_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x15c))
#define NA_SCM_ICR25_ADDRESS                NA_SCM_ICR24_ADDRESS
#define NA_SCM_ICR26_ADDRESS                NA_SCM_ICR24_ADDRESS
#define NA_SCM_ICR27_ADDRESS                NA_SCM_ICR24_ADDRESS

#define NA_SCM_ICR28_ADDRESS                ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x160))
#define NA_SCM_ICR29_ADDRESS				NA_SCM_ICR28_ADDRESS
#define NA_SCM_ICR30_ADDRESS                NA_SCM_ICR28_ADDRESS
#define NA_SCM_ICR31_ADDRESS                NA_SCM_ICR28_ADDRESS

/* signal */
#define SCM_ICR_ACTIVE_LOW      1
#define SCM_ICR_ACTIVE_HIGH     0

/* enable */
#define SCM_ICR_DISABLE     0
#define SCM_ICR_ENABLE      1

/* type */
#define SCM_ICR_IRQ         0
#define SCM_ICR_FIRQ        1

#if defined(NS9360)
/* id */
#define SCM_WATCHDOG_INTERRUPT              0
#define SCM_AHB_BUS_ERROR_INTERRUPT         1
#define SCM_BBUS_AGGREGATE_INTERRUPT        2
#define SCM_RESERVED1_INTERRUPT             3
#define SCM_ETH_RECEIVE_INTERRUPT           4
#define SCM_ETH_TRANSMIT_INTERRUPT          5
#define SCM_ETH_PHY_INTERRUPT               6
#define SCM_LCD_INTERRUPT                   7
#define SCM_SER1RX_INTERRUPT                8
#define SCM_SER1TX_INTERRUPT                9
#define SCM_SER2RX_INTERRUPT                10
#define SCM_SER2TX_INTERRUPT                11
#define SCM_SER3RX_INTERRUPT                12
#define SCM_SER3TX_INTERRUPT                13
#define SCM_I2C_INTERRUPT                   14
#define SCM_BBUS_DMA_INTERRUPT              15
#define SCM_TIMER0_INTERRUPT                16
#define SCM_TIMER1_INTERRUPT                17
#define SCM_TIMER2_INTERRUPT                18
#define SCM_TIMER3_INTERRUPT                19
#define SCM_TIMER4_INTERRUPT                20
#define SCM_TIMER5_INTERRUPT                21
#define SCM_TIMER6_INTERRUPT                22
#define SCM_TIMER7_INTERRUPT                23
#define SCM_RTC_INTERRUPT                   24
#define SCM_USB_HOST_INTERRUPT              25
#define SCM_USB_DEVICE_INTERRUPT            26
#define SCM_IEEE_1284_INTERRUPT             27
#define SCM_EXTERNAL0_INTERRUPT             28
#define SCM_EXTERNAL1_INTERRUPT             29
#define SCM_EXTERNAL2_INTERRUPT             30
#define SCM_EXTERNAL3_INTERRUPT             31

#elif (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

/* id */
#define SCM_WATCHDOG_INTERRUPT              0
#define SCM_AHB_BUS_ERROR_INTERRUPT         1
#define SCM_EXTERNAL_DMA_INTERRUPT          2
#define SCM_CPU_WAKE_INTERRUPT              3
#define SCM_ETH_RECEIVE_INTERRUPT           4
#define SCM_ETH_TRANSMIT_INTERRUPT          5
#define SCM_ETH_PHY_INTERRUPT               6
#define SCM_UART_A_INTERRUPT                7
#define SCM_UART_B_INTERRUPT                8
#define SCM_UART_C_INTERRUPT                9
#define SCM_UART_D_INTERRUPT                10
#define SCM_SPI_INTERRUPT                   11
#define SCM_RESERVED1_INTERRUPT             12
#define SCM_RESERVED2_INTERRUPT             13
#define SCM_A2D_INTERRUPT                   14
#define SCM_EARLY_POWER_LOSS_INTERRUPT      15
#define SCM_I2C_INTERRUPT                   16
#define SCM_RTC_INTERRUPT                   17
#define SCM_TIMER0_INTERRUPT                18
#define SCM_TIMER1_INTERRUPT                19
#define SCM_TIMER2_INTERRUPT                20
#define SCM_TIMER3_INTERRUPT                21
#define SCM_TIMER4_INTERRUPT                22
#define SCM_TIMER5_INTERRUPT                23
#define SCM_TIMER6_INTERRUPT                24
#define SCM_TIMER7_INTERRUPT                25
#define SCM_TIMER8_INTERRUPT                26
#define SCM_TIMER9_INTERRUPT                27
#define SCM_EXTERNAL0_INTERRUPT             28
#define SCM_EXTERNAL1_INTERRUPT             29
#define SCM_EXTERNAL2_INTERRUPT             30
#define SCM_EXTERNAL3_INTERRUPT             31

#else

#define SCM_WATCHDOG_INTERRUPT              0
#define SCM_AHB_BUS_ERROR_INTERRUPT         1
#define SCM_BBUS_AGGREGATE_INTERRUPT        2
#define SCM_JBIG_INTERRUPT                  3
#define SCM_ETH_RECEIVE_INTERRUPT           4
#define SCM_ETH_TRANSMIT_INTERRUPT          5
#define SCM_ETH_PHY_INTERRUPT               6
#define SCM_LCD_INTERRUPT                   7
#define SCM_PCI_BRIDGE_INTERRUPT            8
#define SCM_PCI_ARBITER_INTERRUPT           9
#define SCM_PCI_EXTERNAL0_INTERRUPT         10
#define SCM_PCI_EXTERNAL1_INTERRUPT         11
#define SCM_PCI_EXTERNAL2_INTERRUPT         12
#define SCM_PCI_EXTERNAL3_INTERRUPT         13
#define SCM_I2C_INTERRUPT                   14
#define SCM_RESERVED1_INTERRUPT             15
#define SCM_TIMER0_INTERRUPT                16
#define SCM_TIMER1_INTERRUPT                17
#define SCM_TIMER2_INTERRUPT                18
#define SCM_TIMER3_INTERRUPT                19
#define SCM_TIMER4_INTERRUPT                20
#define SCM_TIMER5_INTERRUPT                21
#define SCM_TIMER6_INTERRUPT                22
#define SCM_TIMER7_INTERRUPT                23
#define SCM_TIMER8_9_INTERRUPT              24
#define SCM_TIMER10_11_INTERRUPT            25
#define SCM_TIMER12_13_INTERRUPT            26
#define SCM_TIMER14_15_INTERRUPT            27
#define SCM_EXTERNAL0_INTERRUPT             28
#define SCM_EXTERNAL1_INTERRUPT             29
#define SCM_EXTERNAL2_INTERRUPT             30
#define SCM_EXTERNAL3_INTERRUPT             31

#endif

#define NA_SCM_ICR0_REG_enable		31, 31
#define NA_SCM_ICR0_REG_invert  	30, 30
#define NA_SCM_ICR0_REG_type		29, 29
#define NA_SCM_ICR0_REG_id		28, 24

#define NA_SCM_ICR1_REG_enable		23, 23
#define NA_SCM_ICR1_REG_invert  	22, 22
#define NA_SCM_ICR1_REG_type		21, 21
#define NA_SCM_ICR1_REG_id		20, 16

#define NA_SCM_ICR2_REG_enable		15, 15
#define NA_SCM_ICR2_REG_invert  	14, 14
#define NA_SCM_ICR2_REG_type		13, 13
#define NA_SCM_ICR2_REG_id		12, 8

#define NA_SCM_ICR3_REG_enable		7, 7
#define NA_SCM_ICR3_REG_invert  	6, 6
#define NA_SCM_ICR3_REG_type		5, 5
#define NA_SCM_ICR3_REG_id		4, 0


 
/*  ???????????????????????????????????????????????????????????????????
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR00_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR01_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR02_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR03_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR04_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR05_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR06_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR07_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR08_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR09_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR10_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR11_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR02_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR13_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR14_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR15_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR16_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR17_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR18_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR19_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR20_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR21_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR22_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR23_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR24_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR25_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR26_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR27_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR28_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR29_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR30_REG;
extern const NA_SCM_ICR_TYPE     NA_SCM_ICR31_REG;

extern const NA_SCM_ICR_TYPE_PTR ICR_registerTable[32];*/

/************************************************/
/* Interrupt Service Routine Register           */
/************************************************/

/* Address Offset */
#define NA_SCM_ISRR_ADDRESS     ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x164))

#define NA_SCM_ISRR_REG_address		31, 0
 

/************************************************/
/* Interrupt Status Active Register             */ 
/************************************************/

/* Address Offset */
#define NA_SCM_ISAR_ADDRESS         ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x168))

#define NA_SCM_ISAR_REG_status		31, 0
 
/************************************************/
/* Interrupt Status Raw Register                */ 
/************************************************/

/* Address Offset */
#define NA_SCM_ISRAWR_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x16c))

#define NA_SCM_ISRAWR_REG_status	31, 0


/************************************************/
/* Timer Interrupt Status Register               */ 
/************************************************/
#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

/*
 * NS9215/10 does not have the timer Interrupt Status Register.  Timer interrupts
 * are not multiplexed, but go directly to interrupt status register.
 */

#else

/* Address Offset */
#define NA_SCM_TISR_ADDRESS        ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x170))

#define NA_SCM_TISR_REG_timer0      0, 0
#define NA_SCM_TISR_REG_timer1      1, 1
#define NA_SCM_TISR_REG_timer2      2, 2
#define NA_SCM_TISR_REG_timer3      3, 3
#define NA_SCM_TISR_REG_timer4      4, 4
#define NA_SCM_TISR_REG_timer5      5, 5
#define NA_SCM_TISR_REG_timer6      6, 6
#define NA_SCM_TISR_REG_timer7      7, 7
#define NA_SCM_TISR_REG_timer8      8, 8
#define NA_SCM_TISR_REG_timer9      9, 9
#define NA_SCM_TISR_REG_timer10     10, 10
#define NA_SCM_TISR_REG_timer11     11, 11
#define NA_SCM_TISR_REG_timer12     12, 12
#define NA_SCM_TISR_REG_timer13     13, 13
#define NA_SCM_TISR_REG_timer14     14, 14
#define NA_SCM_TISR_REG_timer15     15, 15
#define NA_SCM_TISR_REG_reserved	31, 16

#define NA_SCM_TISR_INTERRUPTING     1
#define NA_SCM_TISR_IDLE             0

#endif

/************************************************/
/* Software Watch Dog Configuration Register    */
/************************************************/

/* Address Offset */
#define NA_SCM_SWCR_ADDRESS         ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x174))

/* enable */
#define SCM_SWCR_DISABLE_WATCHDOG       0
#define SCM_SWCR_ENABLE_WATCHDOG        1

/* clearInterrupt */
/*      write 1 then 0 to clear     */

/* response */
#define SCM_SWCR_GENERATE_INTERRUPT     0
#define SCM_SWCR_GENERATE_RESET         1

/* timer */
#define SCM_SWCR_CPU_CLOCK_2            0
#define SCM_SWCR_CPU_CLOCK_4            1
#define SCM_SWCR_CPU_CLOCK_8            2
#define SCM_SWCR_CPU_CLOCK_16           3
#define SCM_SWCR_CPU_CLOCK_32           4
#define SCM_SWCR_CPU_CLOCK_64           5

#define NA_SCM_SWCR_REG_reserved3		31, 8
#define NA_SCM_SWCR_REG_enable			7, 7
#define NA_SCM_SWCR_REG_reserved2		6, 6
#define NA_SCM_SWCR_REG_clearInterrupt          5, 5
#define NA_SCM_SWCR_REG_response		4, 4
#define NA_SCM_SWCR_REG_reserved1		3, 3
#define NA_SCM_SWCR_REG_clockSelect		2, 0
 

/************************************************/
/* Software Watch Dog Timer  Register           */
/************************************************/

/* Address Offset */ 
#define NA_SCM_SWTR_ADDRESS	  ((unsigned long*) (NA_SYS_CONTROL_MODULE_BASE + 0x178))
#define NA_SCM_SWTR_REG_timer		31, 0
 
/************************************************/
/* Clock Configuration Register                 */
/************************************************/

/* Address Offset */
#define NA_SCM_CCR_ADDRESS          ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x17c))

/* all fields */
#define SCM_CCR_DISABLE_CLOCK       0
#define SCM_CCR_ENABLE_CLOCK        1

#ifdef NS9360
#define SCM_CCR_DISABLE_MEM_CLOCK   1
#define SCM_CCR_ENABLE_MEM_CLOCK    0
#else
#define SCM_CCR_DISABLE_MEM_CLOCK   0
#define SCM_CCR_ENABLE_MEM_CLOCK    1
#endif

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define SCM_CCR_FULL_SPEED          0
#define SCM_CCR_DIV_BY_2            1
#define SCM_CCR_DIV_BY_4            2
#define SCM_CCR_DIV_BY_8            3
#define SCM_CCR_DIV_BY_16           4

#define SCM_CCR_AHB_CLOCK           0
#define SCM_CCR_2_TIMES_AHB_CLOCK   1


#define NA_SCM_CCR_REG_clockScaleControl    31, 29
#define NA_SCM_CCR_REG_maxClockScaleControl 28, 26
#define NA_SCM_CCR_REG_cpuClockSelect       25, 25
#define NA_SCM_CCR_REG_reserved1            24, 20
#define NA_SCM_CCR_REG_memoryClock3         19, 19
#define NA_SCM_CCR_REG_memoryClock2         18, 18
#define NA_SCM_CCR_REG_memoryClock1         17, 17
#define NA_SCM_CCR_REG_memoryClock0         16, 16
#define NA_SCM_CCR_REG_reserved2            15, 15
#define NA_SCM_CCR_REG_externalDma          14, 14
#define NA_SCM_CCR_REG_ioHub                13, 13
#define NA_SCM_CCR_REG_rtc                  12, 12
#define NA_SCM_CCR_REG_i2c                  11, 11
#define NA_SCM_CCR_REG_reserved3            10, 10
#define NA_SCM_CCR_REG_aes                  9, 9
#define NA_SCM_CCR_REG_adc                  8, 8
#define NA_SCM_CCR_REG_iop1                 7, 7
#define NA_SCM_CCR_REG_iop0                 6, 6
#define NA_SCM_CCR_REG_spi                  5, 5
#define NA_SCM_CCR_REG_uartd                4, 4
#define NA_SCM_CCR_REG_uartc                3, 3
#define NA_SCM_CCR_REG_uartb                2, 2
#define NA_SCM_CCR_REG_uarta                1, 1
#define NA_SCM_CCR_REG_ethernetMac          0, 0

#else

/* #define NA_SCM_CCR_REG_reserved1        31, 10 only for ns9750 */
#define NA_SCM_CCR_REG_memoryClock3     21, 21
#define NA_SCM_CCR_REG_memoryClock2     20, 20
#define NA_SCM_CCR_REG_memoryClock1     19, 19
#define NA_SCM_CCR_REG_memoryClock0     18, 18
#define NA_SCM_CCR_REG_bbusDma          17, 17
#define NA_SCM_CCR_REG_1284             16, 16
#define NA_SCM_CCR_REG_usbDevice        15, 15
#define NA_SCM_CCR_REG_usbHost          14, 14
#define NA_SCM_CCR_REG_serialCD         13, 13
#define NA_SCM_CCR_REG_serialAB         12, 12
#define NA_SCM_CCR_REG_rtc              11, 11
#define NA_SCM_CCR_REG_i2c              10, 10
#define NA_SCM_CCR_REG_lcdClockSelect   9, 7
#define NA_SCM_CCR_REG_bbus             6, 6
#define NA_SCM_CCR_REG_lcdController    5, 5
#define NA_SCM_CCR_REG_memoryController 4, 4
#define NA_SCM_CCR_REG_pciArbiter       3, 3
#define NA_SCM_CCR_REG_pci              2, 2
#define NA_SCM_CCR_REG_jbig             1, 1
#define NA_SCM_CCR_REG_ethernetMac      0, 0

#endif
/************************************************/
/* Reset and Sleep Register                     */ 
/************************************************/

/* Address Offset */
#define NA_SCM_RSR_ADDRESS          ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x180))

/* all fields */
#define SCM_RSR_RESET_MODULE		0
#define SCM_RSR_ENABLE_MODULE		1

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define SCM_RSR_EXT_RESET_USING_RESET_N     1
#define SCM_RSR_EXT_RESET_USING_SRESET_N    2
#define SCM_RSR_PLL_CHANGE                  3
#define SCM_RSR_SOFTWARE_WATCHDOG_RESET     4
#define SCM_RSR_AHB_BUS_MONITOR_RESET       5

#define NA_SCM_RSR_REG_resetStatus          31, 29
#define NA_SCM_RSR_REG_reserved1            28, 15
#define NA_SCM_RSR_REG_cpuClockSelect       25, 25
#define NA_SCM_RSR_REG_reserved2            24, 20
#define NA_SCM_RSR_REG_memoryClock3         19, 19
#define NA_SCM_RSR_REG_memoryClock2         18, 18
#define NA_SCM_RSR_REG_memoryClock1         17, 17
#define NA_SCM_RSR_REG_memoryClock0         16, 16
#define NA_SCM_RSR_REG_reserved3            15, 15
#define NA_SCM_RSR_REG_externalDma          14, 14
#define NA_SCM_RSR_REG_ioHub                13, 13
#define NA_SCM_RSR_REG_rtc                  12, 12
#define NA_SCM_RSR_REG_i2c                  11, 11
#define NA_SCM_RSR_REG_reserved4            10, 10
#define NA_SCM_RSR_REG_aes                  9, 9
#define NA_SCM_RSR_REG_adc                  8, 8
#define NA_SCM_RSR_REG_iop1                 7, 7
#define NA_SCM_RSR_REG_iop0                 6, 6
#define NA_SCM_RSR_REG_spi                  5, 5
#define NA_SCM_RSR_REG_uartd                4, 4
#define NA_SCM_RSR_REG_uartc                3, 3
#define NA_SCM_RSR_REG_uartb                2, 2
#define NA_SCM_RSR_REG_uarta                1, 1
#define NA_SCM_RSR_REG_ethernetMac          0, 0

#else

#ifdef NS9360
#define NA_SCM_RSR_REG_reserved_3               31, 27
#define NA_SCM_RSR_REG_resetStatus              26, 24
#define NA_SCM_RSR_REG_reserved_2               23, 22
#define NA_SCM_RSR_REG_bbusAggr                 21, 21
#else
#define NA_SCM_RSR_REG_reset                    31, 31
#define NA_SCM_RSR_REG_reserved_2               30, 21
#endif
#define NA_SCM_RSR_REG_i2cWakeUp                20, 20
#define NA_SCM_RSR_REG_i2c                      20, 20
#define NA_SCM_RSR_REG_cpuSleep                 19, 19
#define NA_SCM_RSR_REG_serlCharWakeUp           18, 18
#define NA_SCM_RSR_REG_ethWakeUp                17, 17
#define NA_SCM_RSR_REG_pciInt3WakeUp            16, 16
#define NA_SCM_RSR_REG_reserved_1               15, 7
#define NA_SCM_RSR_REG_bbusTop                  6, 6
#define NA_SCM_RSR_REG_lcdController            5, 5
#define NA_SCM_RSR_REG_memoryController         4, 4
#define NA_SCM_RSR_REG_pciArbiter               3, 3
#define NA_SCM_RSR_REG_pci                      2, 2
#define NA_SCM_RSR_REG_jbig                     1, 1
#define NA_SCM_RSR_REG_ethernetMac              0, 0

#endif


/************************************************/
/* Misc System Configuration Status Register    */
/************************************************/

/* Address Offset */
#define NA_SCM_MSCSR_ADDRESS        ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x184))

#define SCM_MSCSR_NS9250_ID                             0
#define SCM_MSCSR_NS9360_ID                             1
#define SCM_MSCSR_NS9210_ID                             2
#define SCM_MSCSR_NS9215_ID                             3

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define SCM_MSCSR_batteryDead                           0
#define SCM_MSCSR_batteryOkay                           1

#define SCM_MSCSR_bootFromSpi                           0
#define SCM_MSCSR_bootFromFlash                         1

#define SCM_MSCSR_8BitFlash                             0
#define SCM_MSCSR_32BitFlash                            1
#define SCM_MSCSR_32BitFlashB                           2
#define SCM_MSCSR_16BitFlash                            3

#define SCM_MSCSR_8BitSpi                               1
#define SCM_MSCSR_24BitSpi                              2
#define SCM_MSCSR_16BitSpi                              3

#define SCM_MSCSR_littleEndian                          0
#define SCM_MSCSR_bigEndian                             1

#define SCM_MSCSR_allowMisalignedBusAddresses           0
#define SCM_MSCSR_dontAllowMisalignedBusAddresses       1

#define SCM_MSCSR_userModeCannotAccessInternalRegs      0
#define SCM_MSCSR_userModeCanAccessInternalRegs         1

#define NA_SCM_MSCSR_REG_revision                       31, 24
#define NA_SCM_MSCSR_REG_identification                 23, 16
#define NA_SCM_MSCSR_REG_reserved1                      15, 7
#define NA_SCM_MSCSR_REG_rtcBatteryStatus               6, 6
#define NA_SCM_MSCSR_REG_bootMode                       5, 5
#define NA_SCM_MSCSR_REG_bootWidth                      4, 3
#define NA_SCM_MSCSR_REG_endian                         2, 2
#define NA_SCM_MSCSR_REG_misalignBusAddrRsp             1, 1
#define NA_SCM_MSCSR_REG_internalRegAccess              0, 0

#else

#define NA_SCM_MSCSR_REG_revision                       31, 24
#define NA_SCM_MSCSR_REG_reserved_3                     23, 14
#define NA_SCM_MSCSR_REG_bootstrap_rtck_out             13, 13
#define NA_SCM_MSCSR_REG_videoEnable                    12, 12
#define NA_SCM_MSCSR_REG_bootMemory                     11, 11
#define NA_SCM_MSCSR_REG_cs1LanePolarity                10, 10
#define NA_SCM_MSCSR_REG_cs1DataWidth                   9, 8
#define NA_SCM_MSCSR_REG_memCntrlClkMode                7, 7
#define NA_SCM_MSCSR_REG_pciMode                        6, 6
#define NA_SCM_MSCSR_REG_cs1Polarity                    5, 5
#define NA_SCM_MSCSR_REG_reserved_2                     4, 4
#define NA_SCM_MSCSR_REG_endian                         3, 3
#define NA_SCM_MSCSR_REG_misalignBusAddrRsp             2, 2
#define NA_SCM_MSCSR_REG_reserved_1                     1, 1
#define NA_SCM_MSCSR_REG_internalRegAccess              0, 0 
 
#endif


/************************************************/
/*      PLL Configuration Register              */
/************************************************/

/* Address Offset */
#define NA_SCM_PLL_ADDRESS          ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x188))

#define SCM_PLL_ENABLED                         0
#define SCM_PLL_BYPASSED                        1

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

#define NA_SCM_PLL_REG_reserved1                31, 17
#define NA_SCM_PLL_REG_feedbackDivider          16, 8
#define NA_SCM_PLL_REG_bypass                   7, 7
#define NA_SCM_PLL_REG_outputDivider            6, 5
#define NA_SCM_PLL_REG_referenceClockDivider    4, 0

#else

#define NA_SCM_PLL_REG_reserved_2       31, 28
#define NA_SCM_PLL_REG_speed            27, 26
#define NA_SCM_PLL_REG_bypass           25, 25
#define NA_SCM_PLL_REG_FSStatus         24, 23
#define NA_SCM_PLL_REG_ISStatus         22, 21
#define NA_SCM_PLL_REG_NDStatus         20, 16
#define NA_SCM_PLL_REG_SWChange         15, 15
#define NA_SCM_PLL_REG_reserved_1       14, 10
#define NA_SCM_PLL_REG_bypassSW         9, 9
#define NA_SCM_PLL_REG_FSSW             8, 7
#define NA_SCM_PLL_REG_ISSW             6, 5
#define NA_SCM_PLL_REG_NDSW             4, 0
 
#endif
 
/************************************************/
/* Interrupt Level Id Status Register           */
/************************************************/

/* Address Offset */
#define NA_SCM_ILISR_ADDRESS        ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x18C))

#define NA_SCM_ILISR_REG_reserved_1             31, 6
#define NA_SCM_ILISR_REG_interruptLevel         5, 0
 

/* The following is for System Memory Chip Select 0-3 Static Memory Base */
#define NA_SCM_SMCS_STATIC_MEM_BASE(x) ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1F0 + 0x8 * x))

/* The following is for System Memory Chip Select 0-3 Static Memory Mask */

#define NA_SCM_SMCS_STATIC_MEM_MASK(x) ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1F4 + 0x8 * x))


/* The following is for System Memory Chip Select 4 - 7 Dynamic Memory Base */
#define NA_SCM_SMCS_DYNAMIC_MEM_BASE(x) ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1D0 + 0x8 * x))
#define NA_SCM_DYNAMIC_CS_BASE_REG_addr         31, 12
#define CS_BASE_SHIFT_BITS                      12

/* The following is for System Memory Chip Select 4 - 7 Dynamic Memory Mask */
#define NA_SCM_SMCS_DYNAMIC_MEM_MASK(x) ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x1D4 + 0x8 * x))
#define NA_SCM_DYNAMIC_CS_MASK_REG_mask         31, 12
#define NA_SCM_DYNAMIC_CS_MASK_REG_enable       0, 0
#define CS_MASK_SHIFT_BITS                      12

#define NA_SCM_ENABLE_DYNAMIC_CS    1
#define NA_SCM_DISABLE_DYNAMIC_CS   0

/*
 * External Interrupt Control Registers.
 */
#define NA_SCM_EICR_GET_ADDRESS(index)  ((unsigned long volatile *)(NA_SYS_CONTROL_MODULE_BASE + 0x214 + (index*4)))

#define NA_SCM_EICR_0_ADDRESS                   NA_SCM_EICR_GET_ADDRESS(0)
#define NA_SCM_EICR_1_ADDRESS                   NA_SCM_EICR_GET_ADDRESS(1)
#define NA_SCM_EICR_2_ADDRESS                   NA_SCM_EICR_GET_ADDRESS(2)
#define NA_SCM_EICR_3_ADDRESS                   NA_SCM_EICR_GET_ADDRESS(3)

#define NA_SCM_EICR_REG_reserved    31, 4
#define NA_SCM_EICR_REG_sts         3, 3
#define NA_SCM_EICR_REG_clr         2, 2
#define NA_SCM_EICR_REG_plty        1, 1
#define NA_SCM_EICR_REG_lvedg       0, 0


/*******************************************************/
/*          Real Time Clock Control Register           */
/*******************************************************/
#define NA_SCM_RTCMC_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x224))

#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)

/*
 * #defines for standbyStatus and standbyMode.
 */
#define SCM_RTC_STANDBY_MODE                    0
#define SCM_RTC_NORMAL_MODE                     1

/*
 * For clockReadyInterruptStatus and moduleInterruptStatus.
 */
#define SCM_RTC_NOT_INTERRUPTING                0
#define SCM_RTC_INTERRUPTING                    1


#define NA_SCM_RTC_REG_reserved1                    31, 5
#define NA_SCM_RTC_REG_standbyStatus                4, 4
#define NA_SCM_RTC_REG_clockReadyInterruptStatus    3, 3
#define NA_SCM_RTC_REG_moduleInterruptStatus        2, 2
#define NA_SCM_RTC_REG_standbyMode                  1, 1
#define NA_SCM_RTC_REG_clockReadyInterruptClear     0, 0

#else

#define NA_SCM_RTC_clock                    31, 0

#endif


#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/*******************************************************/
/*              Power Management Register              */
/*              NS9215 and NS9210 only                 */
/*******************************************************/
#define NA_SCM_PMR_ADDRESS              ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x228))

#define SCM_PMR_ENABLE                  1
#define SCM_PMR_ARM                     1
#define SCM_PMR_DISABLE                 0

#define NA_SCM_PMR_REG_stopAndResetCpu                      31, 31
#define NA_SCM_PMR_REG_hardwareClockScale                   30, 30
#define NA_SCM_PMR_REG_reserved1                            29, 22
#define NA_SCM_PMR_REG_sdramSelfRefreshControl              21, 21
#define NA_SCM_PMR_REG_wakeInterruptClear                   20, 20
#define NA_SCM_PMR_REG_wakeOnExternalInterrupt3             19, 19
#define NA_SCM_PMR_REG_wakeOnExternalInterrupt2             18, 18
#define NA_SCM_PMR_REG_wakeOnExternalInterrupt1             17, 17
#define NA_SCM_PMR_REG_wakeOnExternalInterrupt0             16, 16
#define NA_SCM_PMR_REG_reserved2                            15, 13
#define NA_SCM_PMR_REG_wakeOnRtcInterrupt                   12, 12
#define NA_SCM_PMR_REG_wakeOnI2cActivity                    11, 11
#define NA_SCM_PMR_REG_reserved3                            10, 6
#define NA_SCM_PMR_REG_wakeOnSpiActivity                    5, 5
#define NA_SCM_PMR_REG_wakeOnUartDCharacterMatch            4, 4
#define NA_SCM_PMR_REG_wakeOnUartCCharacterMatch            3, 3
#define NA_SCM_PMR_REG_wakeOnUartBCharacterMatch            2, 2
#define NA_SCM_PMR_REG_wakeOnUartACharacterMatch            1, 1
#define NA_SCM_PMR_REG_wakeOnEthernetPacket                 0, 0

#endif



#if (PROCESSOR == ns9210) || (PROCESSOR == ns9215)
/*******************************************************/
/*          AHB Bus Activity Status Register           */
/*              NS9215 and NS9210 only                 */
/*******************************************************/
#define NA_SCM_ABASR_ADDRESS            ((unsigned long volatile *) (NA_SYS_CONTROL_MODULE_BASE + 0x22C))


#define NA_SCM_ABASR_REG_activityStatus                     31, 0

#endif

#ifdef __cplusplus
}
#endif

#endif
