
/*****************************************************************************
* Copyright (c) 2004 Digi International Inc., All Rights Reserved
* 
* This software contains proprietary and confidential information of Digi
* International Inc.  By accepting transfer of this copy, Recipient agrees
* to retain this software in confidence, to prevent disclosure to others,
* and to make no use of this software other than that for which it was
* delivered.  This is an unpublished copyrighted work of Digi International
* Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
* prohibited.
* 
* Restricted Rights Legend
*
* Use, duplication, or disclosure by the Government is subject to
* restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
* Technical Data and Computer Software clause at DFARS 252.227-7031 or
* subparagraphs (c)(1) and (2) of the Commercial Computer Software -
* Restricted Rights at 48 CFR 52.227-19, as applicable.
*
* Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
*
*****************************************************************************/
/*
 * $Log: nagpio.h,v $
 * Revision 1.1.2.3  2008/09/17 16:30:10  lzhen
 * Use HW RTS toggle to support CRTSTOGGLE when predelay and postdelay are both zero,
 * in this case, the RTS pin has to use the default GPIO function for RTS. Vantive:        27819
 *
 * Revision 1.2.2.2  2008/09/17 16:01:11  lzhen
 * Use HW RTS toggle to support CRTSTOGGLE when predelay and postdelay are both zero,
 * in this case, the RTS pin has to use the default GPIO function for RTS. Vantive:        27819
 *
 * Revision 1.5  2008/09/17 15:17:46  lzhen
 * Use HW RTS toggle to support CRTSTOGGLE when predelay and postdelay are both zero,
 * in this case, the RTS pin has to use the default GPIO function for RTS. Vantive:        27819
 *
 * Revision 1.4  2008/07/24 14:14:21  whagstro
 * Fixed a redefinition of GPIO_UARTB_RTS
 *
 * Revision 1.3  2008/07/23 15:08:24  whagstro
 * Added the GPIO define for CTS on the n ns9210 and ns9215 based platforms.
 *
 * Revision 1.2  2008/02/12 21:20:03  lzhen
 * On NS9210 and NS9215, RTS in modem_ctrl register can't be controlled by
 *         software while CTS is used for HW flow control. To be able to use CTS to
 *         halt the transmitter, the HW requires the AFE bit in modem_ctrl register
 *         to be 1, but this requirement prohibits us writing to RTS directly.
 *         The work around of this problem is to use RTS pin as GPIO output 0/1 to control RTS.
 *         Refer to NS9215/NS9210 ASIC Errata on RTS.
 *
 * Revision 1.1  2007/07/18 21:16:41  cgordon
 * Renamed Camry-ME platform to connectme9210
 *
 * Revision 1.1  2007/04/11 14:14:20  cgordon
 * Added temporary platform for Connect-ME with Camry.
 *
 * Revision 1.1  2007/02/13 19:54:38  cgordon
 * Initial checkin of NS9210 on NS7520 board platform.
 *
 * Revision 1.3  2006/03/17 19:43:44  vshankar
 * Updated for powersave enhancement
 *
 * Revision 1.2  2005/09/22 22:40:00  lming
 * Changed all includes from " " to < >
 *
 * Revision 1.1  2005/04/28 13:37:41  jfu
 * Added new header file
 *
 * Revision 1.1.2.2  2005/04/28 10:19:30  jfu
 * minor update
 *
 * Revision 1.1.2.1  2005/04/27 23:14:36  jfu
 * Initial files for GPIO I2C expander
 *
 * Revision 1.1.4.4  2005/01/21 17:58:51  markwe
 * Merging code from CDMA dev branch.
 *
 * Revision 1.1.4.3.10.1  2005/01/19 18:31:12  markwe
 * Renamed define GPIO_NOKIA_RST to GPIO_CELLMDM_RST, as the same define applies to all cell modems and is misleading when defined with NOKIA as part of that name.
 *
 * Revision 1.1.4.3  2004/10/21 14:02:38  miken
 * Nokia reset.
 *
 * Revision 1.1.4.2  2004/10/20 11:15:38  jamesp
 * Merging changes needed by new BOOT/POST model into the
 * shared code.
 *
 * Revision 1.1.2.1  2004/07/01 21:14:40  jamesp
 * Moved gpio.c and gpio.h into drivers/gpio.  Moved "arch"
 * high level declarations for gpio stuff into arch/include.
 * Removed obsolete NET+OS header <gpio.h>.  Fixed Makefiles
 * to use files from new locations.
 *
 * Revision 1.1.2.2.2.5  2004/06/28 20:00:48  markw
 * PCI_RST is now on the I2C GPIO pin previously used for MUX_EN, which has been
 * pulled down.
 *
 * Revision 1.1.2.2.2.4  2004/06/25 19:39:00  markw
 * Add GPIO_PCI_RSTN to control PCI reset (output).
 *
 * Revision 1.1.2.2.2.3  2004/06/21 22:44:46  markw
 * Fix indices.
 *
 * Revision 1.1.2.2.2.2  2004/06/21 15:33:46  markw
 * Convert GPIO_INIT to GPIO_SOFTRESET to better describe its function.
 *
 * Revision 1.1.2.2.2.1  2004/06/16 16:15:53  markw
 * Changes to fix Gpio pins on amsterdam.
 *
 * Revision 1.1.2.2  2004/06/14 21:06:35  markw
 * Gpio abstraction for ns7520 products and Amsterdam products.  Now you request
 * gpio pin actions using a function name (e.g. GPIO_MFGO), and this is mapped
 * in a platform-specific way to a processor gpio pin, or an I2C pin, or ....
 *
 */

#ifndef NA_GPIO_H_
#define NA_GPIO_H_

#ifdef __cplusplus
extern "C" {
#endif

/* These are the names of GPIO functions. */
#define GPIO_ERROR_LED    (-1)	  /* error LED           */
#define GPIO_UARTA_RTS	  (-2)    /* RTS for UARTA (ns9210/ns9215 errata fix) */
#define GPIO_UARTB_RTS	  (-3)    /* RTS for UARTB (ns9210/ns9215 errata fix) */
#define GPIO_UARTC_RTS	  (-4)    /* RTS for UARTC (ns9210/ns9215 errata fix) */
#define GPIO_UARTD_RTS	  (-5)    /* RTS for UARTD (ns9210/ns9215 errata fix) */
#define GPIO_UARTA_CTS	  (-6)    /* CTS for UARTA (ns9210/ns9215 errata fix) */
#define GPIO_UARTB_CTS	  (-7)    /* CTS for UARTB (ns9210/ns9215 errata fix) */
#define GPIO_UARTC_CTS	  (-8)    /* CTS for UARTC (ns9210/ns9215 errata fix) */
#define GPIO_UARTD_CTS	  (-9)    /* CTS for UARTD (ns9210/ns9215 errata fix) */


/* Here is a list of the different LEDs.  Each is on when the pin is low.
 *
 * GPIO_ERROR_LED
 *  This is the LED that reports failures by blinking a 3 digit
 *  code.  
 * 
 */

/* This function returns TRUE if the specified function exists on the
 * hardware.
 */
extern int naGpioFunctionExists(int function);

/* Set this gpio pin to be an input.
 * Returns TRUE if successful.
 */
extern int naGpioSetInput(int function);

/* Set this gpio pin to be an output.
 * Returns TRUE if successful.
 */
extern int naGpioSetOutput(int function, unsigned int default_value);

/* Set this gpio pin to be an interrupt.
 * level is 1 for high, 0 for low.
 * edge_trigger is 1 for edge-triggered, 0 for level-triggered.
 * Returns TRUE if successful.
 */
extern int naGpioSetInterrupt(int function, int level, int edge_trigger);

/* Returns 0 or non-zero value of pin.
 * Returns (unsigned long)-1 if unable to get value.
 */
extern unsigned long naGpioGetValue(int function);

/* GPIO pin will be set based on value being 0 or non-zero.  Will be ignored
 * if pin is set as input or interrupt.
 * Returns TRUE if successful.
 */
extern int naGpioSetOutputValue(int function, unsigned long value);

/* Set a gpio pin to a particular function in the gpio mux.  This is only really
 * useful for processor gpio pins, but calling this function abstracts processor
 * differences.
 * Returns TRUE if successful, or FALSE otherwise.
 */
extern int naGpioSetFunction(int function, int gpio_function);

/* GPIO pin will be set to an output with an initial value based on value being
 * 0 or non-zero.  Will atomically change to an output with the desired value
 * if possible.  This attempts to avoid a glitch as the pin becomes an output.
 *
 * Obsoletes GpioSetOutput.
 */
extern int naGpioSetOutputWithValue(int function, unsigned long value);

/*
 * Returns the GPIO control register address and pin associated with the 
 * function. Powersave mode requires GPIO bit to be set in cache, so it 
 * is not easy to use existing naGpioSetOutputValue() function directly.
 *
 */
extern int naGpioGetAddress(int function, unsigned long *addr, unsigned long *pin);

#ifdef __cplusplus
}
#endif

#endif /* GPIO_H_ */

