/*****************************************************************************
* Copyright (c) 2007 Digi International Inc., All Rights Reserved
* 
* This software contains proprietary and confidential information of Digi
* International Inc.  By accepting transfer of this copy, Recipient agrees
* to retain this software in confidence, to prevent disclosure to others,
* and to make no use of this software other than that for which it was
* delivered.  This is an unpublished copyrighted work of Digi International
* Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
* prohibited.
* 
* Restricted Rights Legend
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* restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
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* Restricted Rights at 48 CFR 52.227-19, as applicable.
*
* Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
*
*****************************************************************************/

#if !defined(ns9215_a2d_h) && (PROCESSOR == ns9215) 

#define ns9215_a2d_h

#ifdef __cplusplus
extern "C"
{
#endif

/*ad*
 * Pass this value to 
 * @link naA2dOpen to open the A/D converter on the NS9215 processor.
 *
 * @external
 * @category BSP:Device_Drivers:a2d
 * @since 7.3
*ad*/
#define NS9215_A2D_IDENTIFIER   "NS9215 A/D"


#define NA_A2D_BASE_ADDRESS             (0x90039000)

#define NA_A2D_CONFIG_ADDRESS           ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0000))
#define NA_A2D_CLOCK_CONFIG_ADDRESS     ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0004))
#define NA_A2D_OUTPUT_0_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0008))
#define NA_A2D_OUTPUT_1_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x000C))
#define NA_A2D_OUTPUT_2_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0010))
#define NA_A2D_OUTPUT_3_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0014))
#define NA_A2D_OUTPUT_4_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0018))
#define NA_A2D_OUTPUT_5_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x001C))
#define NA_A2D_OUTPUT_6_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0020))
#define NA_A2D_OUTPUT_7_ADDRESS         ((unsigned long volatile *)(NA_A2D_BASE_ADDRESS + 0x0024))


#define NA_A2D_OUTPUT_ADDRESS(i)        (NA_A2D_OUTPUT_0_ADDRESS + i)
#define NA_A2D_MAX_INPUTS               (8)
#define NA_A2D_RESOLUTION               (12)

/*
 * The values below are approximations.  Assuming a PLL clock
 * of 299827200 Hz, the actual values are 20914 Hz for the minimum
 * clock rate, and 973465 Hz for the maximum.  Note that the 
 * maximum ADC clock rate the H/W supports is 14 MHz, so N must be 
 * at least 10, which is how you get 973465 Hz for the maximum.
 *
 * Note that that the values below are sampling rates, not ADC 
 * clock rates.  It takes 14 ADC clocks to process each sample.
 */
#define NA_A2D_MAX_CLOCK_RATE           (1000000LL)
#define NA_A2D_MIN_CLOCK_RATE           (20000LL)

/*
 * Configuration register for A/D converter.
 */
#define NA_A2D_CONFIG_adcen                     31, 31
#define NA_A2D_CONFIG_instat                    18, 16
#define NA_A2D_CONFIG_intclr                    4, 4
#define NA_A2D_CONFIG_dmaen                     3, 3
#define NA_A2D_CONFIG_sel                       2, 0


/*
 * Clock configuration register.
 */
#define NA_A2D_CLOCK_CONFIG_wait                31, 16
#define NA_A2D_CLOCK_CONFIG_n                   9, 0



/*
 * Output register.
 */
#define NA_A2D_OUTPUT_dout                      11, 0

#define NA_A2D_OUTPUT_MASK                      0xfff



#ifdef __cplusplus
}
#endif

#endif






