/*
 *  Copyright (c) 1996-2007 Digi International Inc., All Rights Reserved
 *
 *  This software contains proprietary and confidential information of Digi
 *  International Inc.  By accepting transfer of this copy, Recipient agrees
 *  to retain this software in confidence, to prevent disclosure to others,
 *  and to make no use of this software other than that for which it was
 *  delivered.  This is an unpublished copyrighted work of Digi International
 *  Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 *  prohibited.
 *
 *  Restricted Rights Legend
 *
 *  Use, duplication, or disclosure by the Government is subject to
 *  restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 *  Technical Data and Computer Software clause at DFARS 252.227-7031 or
 *  subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 *  Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 *  Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 * =======================================================================
 *
 *
 * Edit Date/Ver   Edit Description
 * ==============  ===================================================
 * ESUN 04/16/02   Added "undef fast" to fix a conflicting of "fast" in bsp and fusion.
 * JZW  05/13/03   Replaced all c++ style comments with c style comments
 *                 eliminates compiler warnings under GNU
 * JZW  05/13/04   register address NARM_DBDP5_ADDR was incorrectly defined
 *                 to 0xff9001e0. It should have been defined as 0xff9000e0.
 *
 */

#ifndef _REG_DEF_H
#define _REG_DEF_H
#include <Npttypes.h>

#ifdef __cplusplus
extern "C"
{
#endif

/*
 *#define _narm_read_reg(addr, range, value)		NA_GET_BIT_RANGE(var, range, value)
 *#define narm_read_reg(reg, addr, field, value)	_narm_read_reg(addr, reg ## _ ## field, value)
*/
#if defined(NA_REG_TRACE_ENABLED)
#include "reg_trace.h"
#endif

#if defined(NA_REG_TRACE_ENABLED)
#define _narm_read_reg(addr, range)     reg_trace_read(addr, range, __FILE__, __LINE__)
#define _narm_read_reg32(addr)          reg_trace_read32(addr, 0xffffffff, __FILE__, __LINE__)
#else
#define _narm_read_reg(addr, range)		NA_GET_BIT_RANGE(*addr, range)
#define _narm_read_reg32(addr)          *(addr)
#endif
#define narm_read_reg(reg, addr, field)	_narm_read_reg(addr, reg ## _ ## field)
#define narm_read_reg32(addr)	        _narm_read_reg32(addr)


#if defined(NA_REG_TRACE_ENABLED)
#define _narm_write_reg(addr, range, value)     reg_trace_write(addr, range, value, __FILE__, __LINE__)
#define _narm_write_reg32(addr, value)	        reg_trace_write32(addr, value, 0xffffffff, __FILE__, __LINE__)
#else
#define _narm_write_reg(addr, range, value)		NA_PUT_BIT_RANGE(*addr, range, value)
#define _narm_write_reg32(addr, value)	        *(addr) = (value)
#endif
#define narm_write_reg(reg, addr, field, value)	_narm_write_reg(addr, reg ## _ ## field, value)
#define narm_write_reg32(addr, value)	        _narm_write_reg32(addr, value)

#ifdef fast
#undef fast
#endif
		

#define NETA15         4
#define NETA15_1       5
#define NETA20M        16
#define NETA20UM       0x28
#define NETA40         8
#define NETA40_1       (NETA40+1)
#define NETA40_2       (NETA40+2)
#define NETA40_3       (NETA40+3)
#define NETA40_4       (NETA40+3)
#define NETA50         24
#define NETA50_1       (NETA50 + 1)
#define NETA50_2       (NETA50 + 2)
#define NETA50_3       (NETA50 + 3)
#define NETA50_4       (NETA50 + 3) /* rev number on .4 is same as on .3*/
#define NETA_MAX_REVISIONS  3

/*  BASE address of the hardware registers in the NET+ARM ASIC. */
#define   EFE_BASE 0xFF800000
#define   DMA_BASE 0xFF900000
#define    PC_BASE 0xFFA00000
#define   GEN_BASE 0xFFB00000
#define   MEM_BASE 0xFFC00000
#define   SER_BASE 0xFFD00000
#define CACHE_BASE 0xFFF00000

/* DMA Buffer Descriptor Pointer */
	
#define NARM_DBDP1A_ADDR	((unsigned long volatile *)0xff900000)
#define NARM_DBDP1B_ADDR	((unsigned long volatile *)0xff900020)
#define NARM_DBDP1C_ADDR	((unsigned long volatile *)0xff900040)
#define NARM_DBDP1D_ADDR	((unsigned long volatile *)0xff900060)
#define NARM_DBDP2_ADDR		((unsigned long volatile *)0xff900080)
#define NARM_DBDP3_ADDR		((unsigned long volatile *)0xff9000a0)
#define NARM_DBDP4_ADDR		((unsigned long volatile *)0xff9000c0)
#define NARM_DBDP5_ADDR		((unsigned long volatile *)0xff9000e0)
#define NARM_DBDP6_ADDR		((unsigned long volatile *)0xff900100)
#define NARM_DBDP7_ADDR		((unsigned long volatile *)0xff900120)
#define NARM_DBDP8_ADDR		((unsigned long volatile *)0xff900140)
#define NARM_DBDP9_ADDR		((unsigned long volatile *)0xff900160)
#define NARM_DBDP10_ADDR	((unsigned long volatile *)0xff900180)

/* DMA Buffer Descriptor Pointer */

#define NARM_DBDP_REG_bdp 31, 0

#define DB_WRAP_MASK        0x80000000
#define DB_INT_MASK         0x40000000
#define DB_LAST_MASK        0x20000000



/* DMA Status/Interrupt Enable Register */

#define NARM_DSIER1A_ADDR		((unsigned long volatile *)0xff900014)
#define NARM_DSIER1B_ADDR		((unsigned long volatile *)0xff900034)
#define NARM_DSIER1C_ADDR		((unsigned long volatile *)0xff900054)
#define NARM_DSIER1D_ADDR		((unsigned long volatile *)0xff900074)
#define NARM_DSIER2_ADDR		((unsigned long volatile *)0xff900094)
#define NARM_DSIER3_ADDR		((unsigned long volatile *)0xff9000b4)
#define NARM_DSIER4_ADDR		((unsigned long volatile *)0xff9000d4)
#define NARM_DSIER5_ADDR		((unsigned long volatile *)0xff9000f4)
#define NARM_DSIER6_ADDR		((unsigned long volatile *)0xff900114)
#define NARM_DSIER7_ADDR		((unsigned long volatile *)0xff900134)
#define NARM_DSIER8_ADDR		((unsigned long volatile *)0xff900154)
#define NARM_DSIER9_ADDR		((unsigned long volatile *)0xff900174)
#define NARM_DSIER10_ADDR		((unsigned long volatile *)0xff900194)

/* DMA Status/Interrupt Enable Register */

#define NARM_DSIER_REG_ncip 31, 31
#define NARM_DSIER_REG_ecip 30, 30
#define NARM_DSIER_REG_nrip 29, 29
#define NARM_DSIER_REG_caip 28, 28
#define NARM_DSIER_REG_reserved_1 27, 24
#define NARM_DSIER_REG_ncie 23, 23
#define NARM_DSIER_REG_ecie 22, 22
#define NARM_DSIER_REG_nrie 21, 21
#define NARM_DSIER_REG_caie 20, 20
#define NARM_DSIER_REG_wrap 19, 19
#define NARM_DSIER_REG_idone 18, 18
#define NARM_DSIER_REG_last 17, 17
#define NARM_DSIER_REG_full 16, 16
#define NARM_DSIER_REG_reserved_2 15, 15
#define NARM_DSIER_REG_blen 14, 0

/*
 * NS9750 registers needed by the BSP.
 */
#ifdef BSP_ARM9


    /*
     * Defines for the SCM module GEN config register, we use this register
     * to tell if we are in the debugger or if a restart has occured.
     */
    #define NA_SCM_AHB_GEN_CONFIG_ADDR	((unsigned long volatile *)0xA0900000)
    #define NA_SCM_AHB_GEN_CONFIG_debug         1, 1
    #define NA_SCM_AHB_GEN_CONFIG_restart       2, 2
    #define NA_SCM_AHB_GEN_CONFIG_sleep         3, 3
    #define NA_SCM_AHB_GEN_CONFIG_deep_sleep    4, 4

    #define NA_SCM_CLOCK_BASE_ADDR	((unsigned long volatile *)0xA090017C)
    #define NA_SCM_CLOCK_BASE_usbhost   14, 14 
    #define NA_SCM_CLOCK_BASE_usbdev    15, 15 
    
    /* Defines for the SCM modules static chip selects */
    #define NA_SCM_CS0_BASE_ADDR	((unsigned long volatile *)0xA09001F0)
    #define NA_SCM_CS0_BASE_addr    31, 0

    #define NA_SCM_CS0_MASK_ADDR	((unsigned long volatile *)0xA09001F4)
    #define NA_SCM_CS0_MASK_mask    31, 0

    #define NA_SCM_CS1_BASE_ADDR	((unsigned long volatile *)0xA09001F8)
    #define NA_SCM_CS1_BASE_addr    31, 0

    #define NA_SCM_CS1_MASK_ADDR	((unsigned long volatile *)0xA09001FC)
    #define NA_SCM_CS1_MASK_mask    31, 0

    #define NA_SCM_CS2_BASE_ADDR	((unsigned long volatile *)0xA0900200)
    #define NA_SCM_CS2_BASE_addr      31, 0

    #define NA_SCM_CS2_MASK_ADDR	((unsigned long volatile *)0xA0900204)
    #define NA_SCM_CS2_MASK_mask      31, 0

    #define NA_SCM_CS3_BASE_ADDR	((unsigned long volatile *)0xA0900208)
    #define NA_SCM_CS3_BASE_addr     31, 0

    #define NA_SCM_CS3_MASK_ADDR	((unsigned long volatile *)0xA090020C)
    #define NA_SCM_CS3_MASK_mask      31, 0

    /* Defines for the SCM modules dynamic (RAM) chip selects */
    #define NA_SCM_CS4_BASE_ADDR	((unsigned long volatile *)0xA09001D0)
    #define NA_SCM_CS4_BASE_addr    31, 0

    #define NA_SCM_CS4_MASK_ADDR	((unsigned long volatile *)0xA09001D4)
    #define NA_SCM_CS4_MASK_mask     31, 0

    #define NA_SCM_CS5_BASE_ADDR	((unsigned long volatile *)0xA09001D8)
    #define NA_SCM_CS5_BASE_addr    31, 0

    #define NA_SCM_CS5_MASK_ADDR	((unsigned long volatile *)0xA09001DC)
    #define NA_SCM_CS5_MASK_mask      31, 0

    #define NA_SCM_CS6_BASE_ADDR	((unsigned long volatile *)0xA09001E0)
    #define NA_SCM_CS6_BASE_addr      31, 0

    #define NA_SCM_CS6_MASK_ADDR	((unsigned long volatile *)0xA09001E4)
    #define NA_SCM_CS6_MASK_mask      31, 0

    #define NA_SCM_CS7_BASE_ADDR    ((unsigned long volatile *)0xA09001E8)
    #define NA_SCM_CS7_BASE_addr     31, 0

    #define NA_SCM_CS7_MASK_ADDR     ((unsigned long volatile *)0xA09001EC)
    #define NA_SCM_CS7_MASK_mask     31, 0

    #define NA_SCM_CS_MASK 31, 0
    #define NA_SCM_CS_BASE 31, 0

    /* Defines for SCM module external IRQ registers */
    #define NA_SCM_EXTIRQ0_REG_ADDR    ((unsigned long volatile *)0xA0900214)
    #define NA_SCM_EXTIRQ0_REG_clr     2,2
    
    #define NA_SCM_EXTIRQ1_REG_ADDR    ((unsigned long volatile *)0xA0900218)
    #define NA_SCM_EXTIRQ1_REG_clr     2,2
    
    #define NA_SCM_EXTIRQ2_REG_ADDR    ((unsigned long volatile *)0xA090021c)
    #define NA_SCM_EXTIRQ2_REG_clr     2,2
    
    #define NA_SCM_EXTIRQ3_REG_ADDR    ((unsigned long volatile *)0xA0900220)
    #define NA_SCM_EXTIRQ3_REG_clr     2,2
    
#endif


#ifndef BSP_ARM9
#define DMA_NCIP_BIT 0x8
#define DMA_ECIP_BIT 0x4
#define DMA_NRIP_BIT 0x2
#define DMA_CAIP_BIT 0x1

#define DMA_NCIP_MASK 0x80000000
#define DMA_ECIP_MASK 0x40000000
#define DMA_NRIP_MASK 0x20000000
#define DMA_CAIP_MASK 0x10000000
#define DMA_NRIE_MASK 0x00200000

#define DMA_IP_MASK   0xf0000000
#define DMA_IE_MASK   0x00f00000
#endif

#define NARM_DSIERSI_REG_isrc 31, 28
#define NARM_DSIERSI_REG_reserved_1 27, 24
#define NARM_DSIERSI_REG_ncie 23, 23
#define NARM_DSIERSI_REG_ecie 22, 22
#define NARM_DSIERSI_REG_nrie 21, 21
#define NARM_DSIERSI_REG_caie 20, 20
#define NARM_DSIERSI_REG_wraP 19, 19
#define NARM_DSIERSI_REG_idone 18, 18
#define NARM_DSIERSI_REG_last 17, 17
#define NARM_DSIERSI_REG_full 16, 16
#define NARM_DSIERSI_REG_reserved_2 15, 15
#define NARM_DSIERSI_REG_blen 14, 0
/*
 * the following masks should be applied to NARM_DSIERSI_TYPE, isrc field
 */
#define NCIP_MASK 8	
#define ECIP_MASK 4
#define NRIP_MASK 2
#define CAIP_MASK 1




/* DMA Control Register */

#define NARM_DCR1A_ADDR		((unsigned long volatile *)0xff900010)
#define NARM_DCR1B_ADDR		((unsigned long volatile *)0xff900030)
#define NARM_DCR1C_ADDR		((unsigned long volatile *)0xff900050)
#define NARM_DCR1D_ADDR		((unsigned long volatile *)0xff900070)
#define NARM_DCR2_ADDR		((unsigned long volatile *)0xff900090)
#define NARM_DCR3_ADDR		((unsigned long volatile *)0xff9000b0)
#define NARM_DCR4_ADDR		((unsigned long volatile *)0xff9000d0)
#define NARM_DCR5_ADDR		((unsigned long volatile *)0xff9000f0)
#define NARM_DCR6_ADDR		((unsigned long volatile *)0xff900110)
#define NARM_DCR7_ADDR		((unsigned long volatile *)0xff900130)
#define NARM_DCR8_ADDR		((unsigned long volatile *)0xff900150)
#define NARM_DCR9_ADDR		((unsigned long volatile *)0xff900170)
#define NARM_DCR10_ADDR		((unsigned long volatile *)0xff900190)

#define DCR_FLY_BY_WRITE	0x0
#define DCR_FLY_BY_READ		0x1
#define DCR_MEM_TO_MEM		0x2

#define DCR_32_BIT			0x0
#define	DCR_16_BIT			0x1
#define DCR_8_BIT			0x2

#define BB_100_PERCENT		0
#define BB_75_PERCENT		1
#define BB_50_PERCENT		2
#define BB_25_PERCENT		3

#define BTE_NO_BURST		0
#define BTE_8B_BURST		1
#define BTE_16B_BURST		2

#define REQ_INTERNAL		0
#define REQ_EXTERNAL		1

#define DCR_STATE_IDLE	            0
#define DCR_STATE_LOAD_SRC_ADDR	    1
#define DCR_STATE_LOAD_DEST_ADDR	4
#define DCR_STATE_OP1	            8
#define DCR_STATE_OP2	            10
#define DCR_STATE_UPDATE_DESCR  	20

/* DMA Control Register */

#define NARM_DCR_REG_ce 31, 31
#define NARM_DCR_REG_ca 30, 30
#define NARM_DCR_REG_bb 29, 28
#define NARM_DCR_REG_mode 27, 26
#define NARM_DCR_REG_bte 25, 24
#define NARM_DCR_REG_req 23, 23
#define NARM_DCR_REG_reserved_1 22, 22
#define NARM_DCR_REG_sinc 21, 21
#define NARM_DCR_REG_dinc 20, 20
#define NARM_DCR_REG_reserved_2 19, 18
#define NARM_DCR_REG_size 17, 16
#define NARM_DCR_REG_state 15, 10
#define NARM_DCR_REG_index 9, 0

#define NARM_GET_DB_INDEX(dcr_addr)  (narm_read_reg (NARM_DCR_REG, dcr_addr, index) >> 3)

/* ENI General Control Register */

/*#define NARM_ENI_GCR_ADDR		((unsigned long volatile *)0xffa00000)*/		/* ENI General Control Register */
#define NARM_GCR_ADDR		((unsigned long volatile *)0xffa00000)		/* ENI General Control Register */

#define GCR_INIT_STATE				0x0
#define CR_INIT_STATEG				0x0
#define GCR_GPIO                    0x0
#define GCR_IEEE_1284				0x1
#define GCR_ENI_SHARED_RAM_16_BIT	0x4
#define GCR_ENI_SHARED_RAM_8_BIT	0x5
#define GCR_ENI_FIFO_16_BIT			0x6
#define GCR_ENI_FIFO_8_BIT			0x7

#define NARM_GCR_REG_erx 31, 31
#define NARM_GCR_REG_erxdma 30, 30
#define NARM_GCR_REG_reserved_1 29, 29
#define NARM_GCR_REG_reserved_2 28, 28
#define NARM_GCR_REG_erxreg 27, 27
#define NARM_GCR_REG_erfifoh 26, 26
#define NARM_GCR_REG_reserved_3 25, 25
#define NARM_GCR_REG_ebei 24, 24
#define NARM_GCR_REG_etx 23, 23
#define NARM_GCR_REG_etxdma 22, 22
#define NARM_GCR_REG_reserved_4 21, 20
#define NARM_GCR_REG_etxreg 19, 19
#define NARM_GCR_REG_etfifoh 18, 18
#define NARM_GCR_REG_reserved_5 17, 16
#define NARM_GCR_REG_reserved_6 15, 13
#define NARM_GCR_REG_enidiag 12, 12
#define NARM_GCR_REG_reserved_7 11, 3
#define NARM_GCR_REG_enimode 2, 0

/* General Status Register */

#define NARM_GSR_ADDR		((unsigned long volatile *)0xffa00004)		/* General Status Register */

/* ENI General Status Register */

#define NARM_ESR_REG_reserved_1 31, 31
#define NARM_ESR_REG_reserved_2 30, 30
#define NARM_ESR_REG_rxfdb 29, 28
#define NARM_ESR_REG_rxregr 27, 27
#define NARM_ESR_REG_rxfifoh 26, 26
#define NARM_ESR_REG_reserved_3 25, 25
#define NARM_ESR_REG_bei 24, 24
#define NARM_ESR_REG_reserved_4 23, 23
#define NARM_ESR_REG_reserved_5 22, 22
#define NARM_ESR_REG_reserved_6 21, 21
#define NARM_ESR_REG_reserved_7 20, 20
#define NARM_ESR_REG_txrege 19, 19
#define NARM_ESR_REG_txfifoh 18, 18
#define NARM_ESR_REG_reserved_8 17, 17
#define NARM_ESR_REG_txfifoe 16, 16
#define NARM_ESR_REG_reserved_9 15, 0

/* ENI Control Register */

#define NARM_ECR_ADDR		((unsigned long volatile *)0xffa00030)		/* ENI Control Register */

/* ENI Control Register */

#define NARM_ECR_REG_reserved 31, 16
#define NARM_ECR_REG_wait 15, 13
#define NARM_ECR_REG_dmae2 12, 12
#define NARM_ECR_REG_fast 11, 11
#define NARM_ECR_REG_dpack 10, 10
#define NARM_ECR_REG_psio 9, 9
#define NARM_ECR_REG_kyoint 8, 8
#define NARM_ECR_REG_intp 7, 7
#define NARM_ECR_REG_wr_oc 6, 6
#define NARM_ECR_REG_dint2 5, 5
#define NARM_ECR_REG_i_oc 4, 4
#define NARM_ECR_REG_dmae 3, 3
#define NARM_ECR_REG_irqen 2, 2
#define NARM_ECR_REG_epack 1, 1
#define NARM_ECR_REG_pulint 0, 0


/* ENI Shared RAM Address Register */
#define NARM_ESRAR_ADDR		((unsigned long volatile *)0xffa00038)		/* ENI Shared RAM Address Register */

#define ESRAR_RAMSIZE_64K			0x0
#define ESRAR_RAMSIZE_32K			0x8
#define ESRAR_RAMSIZE_16K			0xc
#define ESRAR_RAMSIZE_8K			0xe
#define ESRAR_RAMSIZE_4K			0xf


#define NARM_ESRAR_REG_base 31, 12
#define NARM_ESRAR_REG_reserved_1 11, 9
#define NARM_ESRAR_REG_enable 8, 8
#define NARM_ESRAR_REG_reserved_2 7, 4
#define NARM_ESRAR_REG_ramsize 3, 0

/* Structure of ENI Shared Register */

#define NARM_ESHR_ADDR		((unsigned long volatile *)0xffa0003C)		/* ENI Shared Register */
/*#define NARM_ESHR_OFFSET	0x10000 */
#define NARM_ESHR_OFFSET	0x40000

#define SINTP2_PINT1		0
#define	SINTP2_PINT2		1

#define NARM_ESHR_REG_reserved 31, 8
#define NARM_ESHR_REG_rstio 7, 7
#define NARM_ESHR_REG_intiof 6, 6
#define NARM_ESHR_REG_emmint 5, 5
#define NARM_ESHR_REG_ehwint 4, 4
#define NARM_ESHR_REG_sintp2 3, 3
#define NARM_ESHR_REG_vdaint 2, 2
#define NARM_ESHR_REG_stsint 1, 1
#define NARM_ESHR_REG_clrint 0, 0


/* FIFO Mode Data Register */

/* Address of shared RAM + NARM_FMDR_OFFSET */
/*#define NARM_FMDR_OFFSET	0x10004 */
#define NARM_FMDR_OFFSET	0x40004

#define NARM_FMDR_REG_data 15, 0

/* FIFO Mode Mask / Status Register */

/* #define NARM_FMSR_OFFSET	0x10008 */
#define NARM_FMSR_OFFSET	0x40008

#define NARM_FMSR_REG_reserved_1 15, 15
#define NARM_FMSR_REG_reserved_2 14, 14
#define NARM_FMSR_REG_rdbufrdy 13, 13
#define NARM_FMSR_REG_wrbufemp 12, 12
#define NARM_FMSR_REG_edrdbufrdy 11, 11
#define NARM_FMSR_REG_edwrbufemp 10, 10
#define NARM_FMSR_REG_eirdbufrdy 9, 9
#define NARM_FMSR_REG_eiwrbufemp 8, 8
#define NARM_FMSR_REG_reserved_3 7, 0

/* Port Register */

#define NARM_PORTX_REG_mode 31, 24
#define NARM_PORTX_REG_dir 23, 16
#define NARM_PORTX_REG_reserved 15, 8
#define NARM_PORTX_REG_data 7, 0


#define NARM_PORTA_ADDR		((unsigned long volatile *)0xffb00020)
#define NARM_PORTB_ADDR		((unsigned long volatile *)0xffb00024)
#define NARM_PORTC_ADDR		((unsigned long volatile *)0xffb00028)
#define NARM_PORTD1_ADDR        ((unsigned long volatile *)0xFFA00040)
#define NARM_PORTD2_ADDR        ((unsigned long volatile *)0xFFA00044)
#define NARM_PORTF_ADDR         ((unsigned long volatile *)0xFFA00048)
#define NARM_PORTG_ADDR         ((unsigned long volatile *)0xFFA0004C)
#define NARM_PORTH_ADDR         ((unsigned long volatile *)0xFFA00050)

#define NARM_PORT_MODE		    0xFF000000
#define NARM_PORT_DIR		    0x00FF0000
#define NARM_PORT_SF		    0x0000FF00
#define NARM_PORT_DATA		    0x000000FF


/* Interrupt Enable Register */

#define NARM_IER_ADDR		((unsigned long volatile *)0xffb00030)

#define IER_DMA1_BIT	31
#define IER_DMA2_BIT	30
#define IER_DMA3_BIT	29
#define IER_DMA4_BIT	28
#define IER_DMA5_BIT	27
#define IER_DMA6_BIT	26
#define IER_DMA7_BIT	25
#define IER_DMA_BIT	24
#define IER_DMA9_BIT	23
#define IER_DMA10_BIT	22

/* Interrupt Enable Register */

#define NARM_IER_REG_dma1 31, 31
#define NARM_IER_REG_dma2 30, 30
#define NARM_IER_REG_dma3 29, 29
#define NARM_IER_REG_dma4 28, 28
#define NARM_IER_REG_dma5 27, 27
#define NARM_IER_REG_dma6 26, 26
#define NARM_IER_REG_dma7 25, 25
#define NARM_IER_REG_dma8 24, 24
#define NARM_IER_REG_dma9 23, 23
#define NARM_IER_REG_dma10 22, 22
#define NARM_IER_REG_eni_port1 21, 21
#define NARM_IER_REG_eni_port2 20, 20
#define NARM_IER_REG_eni_port3 19, 19
#define NARM_IER_REG_eni_port4 18, 18
#define NARM_IER_REG_dma11 21, 21
#define NARM_IER_REG_dma12 20, 20
#define NARM_IER_REG_dma13 19, 19
#define NARM_IER_REG_enet_rx 17, 17
#define NARM_IER_REG_enet_tx 16, 16
#define NARM_IER_REG_ser1_rx 15, 15
#define NARM_IER_REG_ser1_tx 14, 14
#define NARM_IER_REG_ser2_rx 13, 13
#define NARM_IER_REG_ser2_tx 12, 12
#define NARM_IER_REG_usb 11, 11
#define NARM_IER_REG_reserved_2 10, 10
#define NARM_IER_REG_reserved_3 9, 9
#define NARM_IER_REG_reserved_4 8, 8
#define NARM_IER_REG_reserved_5 7, 7
#define NARM_IER_REG_watch_dog 6, 6
#define NARM_IER_REG_timer1 5, 5
#define NARM_IER_REG_timer2 4, 4
#define NARM_IER_REG_portc_pc3 3, 3
#define NARM_IER_REG_portc_pc2 2, 2
#define NARM_IER_REG_portc_pc1 1, 1
#define NARM_IER_REG_portc_pc0 0, 0

#define NARM_T1CR_ADDR      ((unsigned long volatile *)0xffb00010) /* Timer 1 Control register address */
#define NARM_T2CR_ADDR      ((unsigned long volatile *)0xffb00018) /* Timer 2 Control register address */
#define NARM_T1SR_ADDR      ((unsigned long volatile *)0xffb00014) /* Timer 1 Status register address */
#define NARM_T2SR_ADDR      ((unsigned long volatile *)0xffb0001C) /* Timer 2 Status register address */

/*
 * Fields in timer control register.
 */
#define NARM_TMRCR_REG_te       31, 31      /* timer enable*/
#define NARM_TMRCR_REG_tie      30, 30      /* timer interrupt enable*/
#define NARM_TMRCR_REG_tiro     29, 29      /* timer interrupt mode*/
#define NARM_TMRCR_REG_tpre     28, 28      /* timer prescaler*/
#define NARM_TMRCR_REG_tclk     27, 27      /* timer clock source*/
#define NARM_TMRCR_REG_itc      26, 0       /* initial count */

#define TIMER_ENABLE                    1
#define TIMER_RESET_AND_DISABLE         0

#define TIMER_ENABLE_INTERRUPT          1
#define TIMER_DISABLE_INTERRUPT         0

#define TIMER_NORMAL_INTERRUPT          0
#define TIMER_FAST_INTERRUPT            1

#define TIMER_NO_PRESCALER              0
#define TIMER_512_PRESCALER             1

#define TIMER_CRYSTAL_CLOCK             0
#define TIMER_SYSCLK_CLOCK              1



/*
 * Fields in timer status register.
 */
#define NARM_TMRSR_REG_tip      30, 30
#define NARM_TMRSR_REG_ctc      26, 0

#define TIMER_INTERRUPT_PENDING         1
#define TIMER_CLEAR_PENDING_INTERRUPT   1



/* Memory Module Configuration Register */

#define NARM_MMCR_ADDR      ((unsigned long volatile *)0xffc00000)

/* Memory Module Configuration Register */

#define NARM_MMCR_REG_rfcnt 31, 24
#define NARM_MMCR_REG_refen 23, 23
#define NARM_MMCR_REG_rcyc 22, 21
#define NARM_MMCR_REG_amux 20, 20
#define NARM_MMCR_REG_a27 19, 19
#define NARM_MMCR_REG_a26 18, 18
#define NARM_MMCR_REG_a25 17, 17
#define NARM_MMCR_REG_amux2 16, 16
#define NARM_MMCR_REG_reserved 15, 0

#define NARM_MMCR_RCYC_8_BCLK       0
#define NARM_MMCR_RCYC_6_BCLK       1
#define NARM_MMCR_RCYC_5_BCLK       2
#define NARM_MMCR_RCYC_4_BCLK       3





/* Chip Select Base Address Register */

#define NARM_CSAR0_ADDR                 ((unsigned long volatile *)0xffc00010)
#define NARM_CSAR1_ADDR                 ((unsigned long volatile *)0xffc00020)
#define NARM_CSAR2_ADDR                 ((unsigned long volatile *)0xffc00030)
#define NARM_CSAR3_ADDR                 ((unsigned long volatile *)0xffc00040)
#define NARM_CSAR4_ADDR                 ((unsigned long volatile *)0xffc00050)

/* Chip Select Base Address Register */

#define NARM_CSAR_REG_base 31, 12
#define NARM_CSAR_REG_pgsize 11, 10
#define NARM_CSAR_REG_dmode 9, 8
#define NARM_CSAR_REG_dmuxs 7, 7
#define NARM_CSAR_REG_reserved_2 6, 6
#define NARM_CSAR_REG_dmuxm 5, 5
#define NARM_CSAR_REG_idle 4, 4
#define NARM_CSAR_REG_drsel 3, 3
#define NARM_CSAR_REG_burst 2, 2
#define NARM_CSAR_REG_wp 1, 1
#define NARM_CSAR_REG_v 0, 0

#define NARM_CSAR_BASE_MASK             0xfffff000
#define NARM_CSAR_V_MASK                0x00000001

#define CSAR_PGSIZE_64_BYTES            0x0
#define CSAR_PGSIZE_32_BYTES            0x1
#define CSAR_PGSIZE_16_BYTES            0x2
#define CSAR_PGSIZE_8_BYTES             0x3

#define CSAR_DMODE_FAST_PAGE            0x0
#define CSAR_DMODE_EDO_DRAM             0x1
#define CSAR_DMODE_SYNC_DRAM            0x2
#define CSAR_DMODE_RESERVED             0x3


/* Chip Select Option Register */

#define NARM_CSOR0_ADDR                 ((unsigned long volatile *)0xffc00014)
#define NARM_CSORB0_ADDR                ((unsigned long volatile *)0xffc00018)
#define NARM_CSOR1_ADDR                 ((unsigned long volatile *)0xffc00024)
#define NARM_CSORB1_ADDR                ((unsigned long volatile *)0xffc00028)
#define NARM_CSOR2_ADDR                 ((unsigned long volatile *)0xffc00034)
#define NARM_CSORB2_ADDR                ((unsigned long volatile *)0xffc00038)
#define NARM_CSOR3_ADDR                 ((unsigned long volatile *)0xffc00044)
#define NARM_CSORB3_ADDR                ((unsigned long volatile *)0xffc00048)
#define NARM_CSOR4_ADDR                 ((unsigned long volatile *)0xffc00054)
#define NARM_CSORB4_ADDR                ((unsigned long volatile *)0xffc00058)

#define CSOR_32_BIT_PORT_SIZE			0x0
#define CSOR_16_BIT_PORT_SIZE			0x1
#define CSOR_8_BIT_PORT_SIZE			0x2
#define CSOR_32_BIT_PORT_EXTERNAL_DATA	0x3

#define CSOR_DMUXM_10_CAS               0x0
#define CSOR_DMUXM_8_CAS                0x1

#define CSOR_FAST_PAGE_DRAM		0
#define CSOR_EDO DRAM			1
#define CSOR_SYNCHRONOUS_DRAM	2

#define CSOR_MASK_ADDRESS		0xfff00000

/* Chip Select Option Register */

#define NARM_CSOR_REG_mask 31, 12
#define NARM_CSOR_REG_wait 11, 8
#define NARM_CSOR_REG_bcyc 7, 6
#define NARM_CSOR_REG_bsize 5, 4
#define NARM_CSOR_REG_ps 3, 2
#define NARM_CSOR_REG_rsync 1, 1
#define NARM_CSOR_REG_wsync 0, 0
#define NARM_CSOR_BSIZE_SDRAM_SETUP     0x3




/* Chip Select Option Register B */

#define NARM_CSORB_REG_reserved 31, 6
#define NARM_CSORB_REG_wait 5, 4
#define NARM_CSORB_REG_bcyc 3, 2
#define NARM_CSORB_REG_sync 1, 0

/* added 2/26/02 SW */

/*
 * GEN Module
 * System Control Register TBD
 *#define   GEN_BASE 0xFFB00000
 */
/* General Module System Control Register */

#define NARM_GSCR_REG_lendian 31, 31
#define NARM_GSCR_REG_bspeed 30, 29
#define NARM_GSCR_REG_bclkd 28, 28
#define NARM_GSCR_REG_reserved1 27, 25
#define NARM_GSCR_REG_swe 24, 24
#define NARM_GSCR_REG_swri 23, 22
#define NARM_GSCR_REG_swt 21, 20
#define NARM_GSCR_REG_reserved2 19, 19
#define NARM_GSCR_REG_bme 18, 18
#define NARM_GSCR_REG_bmt 17, 16
#define NARM_GSCR_REG_user 15, 15
#define NARM_GSCR_REG_buser 14, 14
#define NARM_GSCR_REG_iarb 13, 13
#define NARM_GSCR_REG_dmatst 12, 12
#define NARM_GSCR_REG_tea_last 11, 11
#define NARM_GSCR_REG_misalign 10, 10
#define NARM_GSCR_REG_cache 9, 9
#define NARM_GSCR_REG_wb 8, 8
#define NARM_GSCR_REG_cinit 7, 7
#define NARM_GSCR_REG_dmarst 6, 6
#define NARM_GSCR_REG_bsync 5, 4
#define NARM_GSCR_REG_reserved3 3, 0

#define NARM_GSCR_ADDR		((volatile  unsigned long *)0xffb00000)

/* General Module System Status Register */

#define NARM_GSSR_REG_rev 31, 24
#define NARM_GSSR_REG_ext 23, 23
#define NARM_GSSR_REG_pow 22, 22
#define NARM_GSSR_REG_sw 21, 21
#define NARM_GSSR_REG_rstio 20, 20
#define NARM_GSSR_REG_reserved1 19, 17
#define NARM_GSSR_REG_lock 16, 16
#define NARM_GSSR_REG_reserved2 15, 11
#define NARM_GSSR_REG_gen_id1 10, 0



#define NARM_GSSR_ADDR		((volatile  unsigned long *)0xffb00004)	

/* PLL Control Register */
#define NARM_GPLR_REG_reserved1 31, 28
#define NARM_GPLR_REG_pllcnt 27, 24
#define NARM_GPLR_REG_reserved2 23, 12
#define NARM_GPLR_REG_pllval 11, 0

#define NARM_GPLR_ADDR		((unsigned long volatile *)0xffb00008)

/*PLL Setting Register, for 20UM chips, read only */
#define NARM_GPLSR_REG_reserved1 31, 9
#define NARM_GPLSR_REG_is 8, 7
#define NARM_GPLSR_REG_fs 6, 5
#define NARM_GPLSR_REG_nd 4, 0

#define NARM_GPLSR_ADDR		((unsigned long volatile *)0xffb00040)



/* Software Service Register */
#define NARM_GSWSR_ADDR          ((volatile  unsigned long *)0xffb0000C)
/* Cache Control Register 0 */
#define NARM_GCCR0_ADDR          ((volatile  unsigned long *)0xffb00040)
/* Cache Control Register 1 */
#define NARM_GCCR1_ADDR          ((volatile  unsigned long *)0xffb00044)


/*
 * EFE module
 * Ethernet General Control Register
 * {{
 */

#define NARM_EIM_MII              0x0
#define NARM_EIM_LEVEL1_ENDEC     0x2
#define NARM_EIM_SEEQ_ENDEC       0x3

#define NARM_ETXWM_100            0x3
#define NARM_ETXWM_75             0x2
#define NARM_ETXWM_50             0x1
#define NARM_ETXWM_25             0x0

#define NARM_EXINT_MII            0x0
#define NARM_EXINT_TPPMD          0x1
#define NARM_EXINT_ENDEC          0x2

#define NARM_EUTP                 0x1
#define NARM_ESTP                 0x0

#define NARM_AUITP_AUTO           0x0
#define NARM_AUI_PORT             0x1
#define NARM_TP_PORT              0x2


/* Ethernet General Control Register */

#define NARM_EGCR_REG_erx 31, 31
#define NARM_EGCR_REG_erxdma 30, 30
#define NARM_EGCR_REG_erxlng 29, 29
#define NARM_EGCR_REG_erxsht 28, 28
#define NARM_EGCR_REG_erxreg 27, 27
#define NARM_EGCR_REG_erfifoh 26, 26
#define NARM_EGCR_REG_erxbr 25, 25
#define NARM_EGCR_REG_erxbad 24, 24
#define NARM_EGCR_REG_etx 23, 23
#define NARM_EGCR_REG_etxdma 22, 22
#define NARM_EGCR_REG_etxwm 21, 20
#define NARM_EGCR_REG_etxreg 19, 19
#define NARM_EGCR_REG_etfifoh 18, 18
#define NARM_EGCR_REG_etxbc 17, 17
#define NARM_EGCR_REG_efulld 16, 16
#define NARM_EGCR_REG_mode 15, 14
#define NARM_EGCR_REG_reserved1 13, 13
#define NARM_EGCR_REG_rxcinv 12, 12
#define NARM_EGCR_REG_txcinv 11, 11
#define NARM_EGCR_REG_pna 10, 10
#define NARM_EGCR_REG_reserved2 9, 8
#define NARM_EGCR_REG_pdn 7, 7
#define NARM_EGCR_REG_ctype 6, 5
#define NARM_EGCR_REG_lnk_dis 4, 4
#define NARM_EGCR_REG_lpbk 3, 3
#define NARM_EGCR_REG_utp_stp 2, 2
#define NARM_EGCR_REG_reserved3 1, 0


#define NARM_EGCR50_REG_reserved1 31, 14
#define NARM_EGCR50_REG_lb 13, 13
#define NARM_EGCR50_REG_reserved2 12, 0


#define NARM_EGCR20UM_REG_reserved1 31, 10
#define NARM_EGCR20UM_REG_mac_reset 9, 9
#define NARM_EGCR20UM_REG_itxa 8, 8
#define NARM_EGCR20UM_REG_reserved2 7, 2
#define NARM_EGCR20UM_REG_exint 1, 0


#define NARM_EGCR_ADDR		((unsigned long volatile *)0xff800000)		/* Ethernet General Control Register */
/*
 * }}
 *
 * {{
 * Ethernet General Status Register
 * {{
 */
/* Ethernet General Status Register */

#define NARM_EGSR_REG_reserved1 31, 30
#define NARM_EGSR_REG_rxfdb 29, 28
#define NARM_EGSR_REG_rxregr 27, 27
#define NARM_EGSR_REG_rxfifoh 26, 26
#define NARM_EGSR_REG_rxbr 25, 25
#define NARM_EGSR_REG_rxskip 24, 24
#define NARM_EGSR_REG_reserved2 23, 20
#define NARM_EGSR_REG_txrege 19, 19
#define NARM_EGSR_REG_txfifoh 18, 18
#define NARM_EGSR_REG_txbc 17, 17
#define NARM_EGSR_REG_txfifoe 16, 16
#define NARM_EGSR_REG_fulld 15, 15
#define NARM_EGSR_REG_reserved3 14, 14
#define NARM_EGSR_REG_mansense 13, 13
#define NARM_EGSR_REG_ctype 12, 12
#define NARM_EGSR_REG_linkpul 11, 11
#define NARM_EGSR_REG_automan 10, 10
#define NARM_EGSR_REG_reserved4 9, 0

#define NARM_EGSR_ADDR		((unsigned long volatile *)0xff800004)		/* Ethernet General Status Register */
#define NARM_ETSR_ADDR      ((unsigned long volatile *)0xff800010)
/* }} */



/* Ethernet MAC configuration registers */
/* Ethernet MAC Configuration Registers */

#define NARM_EMACCFR_REG_reserved1 31, 16
#define NARM_EMACCFR_REG_srst 15, 15
#define NARM_EMACCFR_REG_intlb 14, 14
#define NARM_EMACCFR_REG_tstmd 13, 12
#define NARM_EMACCFR_REG_reserved2 11, 6
#define NARM_EMACCFR_REG_nobo 5, 5
#define NARM_EMACCFR_REG_rtryl 4, 4
#define NARM_EMACCFR_REG_crcen 3, 3
#define NARM_EMACCFR_REG_paden 2, 2
#define NARM_EMACCFR_REG_fulld 1, 1
#define NARM_EMACCFR_REG_hugen 0, 0


#define NARM_EMACCFR_ADDR		((unsigned long volatile *)0xff800400)	

#define NARM_EMAC1CFR_ADDR		((unsigned long volatile *)0xff800400)		/* Ethernet General Status Register */

#define NARM_EMAC1CFR_REG_reserved1 31, 16
#define NARM_EMAC1CFR_REG_srst 15, 15
#define NARM_EMAC1CFR_REG_reserved2 14, 1
#define NARM_EMAC1CFR_REG_rxen 0, 0

#define NARM_EMAC2CFR_REG_reserved1 31, 15
#define NARM_EMAC2CFR_REG_edefer 14, 14
#define NARM_EMAC2CFR_REG_backp 13, 13
#define NARM_EMAC2CFR_REG_nobo 12, 12
#define NARM_EMAC2CFR_REG_reserved2 11, 10
#define NARM_EMAC2CFR_REG_longp 9, 9
#define NARM_EMAC2CFR_REG_purep 8, 8
#define NARM_EMAC2CFR_REG_autop 7, 7
#define NARM_EMAC2CFR_REG_vlanp 6, 6
#define NARM_EMAC2CFR_REG_paden 5, 5
#define NARM_EMAC2CFR_REG_crcen 4, 4
#define NARM_EMAC2CFR_REG_delcrc 3, 3
#define NARM_EMAC2CFR_REG_hugen 2, 2
#define NARM_EMAC2CFR_REG_flenc 1, 1
#define NARM_EMAC2CFR_REG_fulld 0, 0

#define NARM_EMAC2CFR_ADDR		((unsigned long volatile *)0xff800404)		/* Ethernet General Status Register */


#define NARM_EPCSCR_REG_reserved1 31, 10
#define NARM_EPCSCR_REG_exint 9, 8
#define NARM_EPCSCR_REG_reserved2 7, 3
#define NARM_EPCSCR_REG_clks 2, 2
#define NARM_EPCSCR_REG_jabber 1, 1
#define NARM_EPCSCR_REG_nocfr 0, 0



#define NARM_EPCSCR_ADDR            ((unsigned long volatile *)0xff800408)

#define NARM_EPHYSR_REG_reserved1 31, 13
#define NARM_EPHYSR_REG_phymode 12, 12
#define NARM_EPHYSR_REG_reserved2 11, 6
#define NARM_EPHYSR_REG_nocrf 5, 5
#define NARM_EPHYSR_REG_reserved3 4, 2
#define NARM_EPHYSR_REG_jabber 1, 1
#define NARM_EPHYSR_REG_endec 0, 0

#define NARM_EPHYSR_ADDR            ((unsigned long volatile *)0xff800418)

/*
 * {{
 * Ethernet MII Configuration Register
*/

#define NARM_EMCFG_REG_reserved1 31, 16
#define NARM_EMCFG_REG_rmiim 15, 15
#define NARM_EMCFG_REG_reserved2 14, 5
#define NARM_EMCFG_REG_clks 4, 2
#define NARM_EMCFG_REG_spre 1, 1
#define NARM_EMCFG_REG_scani 0, 0


#define NARM_EMCFG_ADDR		((unsigned long volatile *)0xff800420)


/* Ethernet MII Command Register */

#define NARM_EMIC_REG_reserved 31, 2
#define NARM_EMIC_REG_scan 1, 1
#define NARM_EMIC_REG_rstat 0, 0

#define NARM_EMIC50_ADDR	((unsigned long volatile *)0xff800540)		/* Ethernet MII Command Register */ /* }} */
#define NARM_EMIC20UM_ADDR	((unsigned long volatile *)0xff800424)		/* Ethernet MII Command Register */


/* Ethernet MII Address Register */

#define NARM_EMAR_REG_reserved 31, 16
#define NARM_EMAR_REG_madr 15, 0

#define NARM_EMAR50_ADDR	((unsigned long volatile *)0xff800544)		/* Ethernet MII Address Register */
#define NARM_EMAR20UM_ADDR	((unsigned long volatile *)0xff800428)		/* Ethernet MII Address Register */

/* Ethernet MII Write Data Register */

#define NARM_EMWT_REG_reserved 31, 16
#define NARM_EMWT_REG_mwtd 15, 0

#define NARM_EMWT50_ADDR	((unsigned long volatile *)0xff800548)		/* Ethernet MII Write Data Register */
#define NARM_EMWT20UM_ADDR	((unsigned long volatile *)0xff80042C)		/* Ethernet MII Write Data Register */


/* Ethernet MII Read Data Register */

#define NARM_EMRD_REG_reserved 31, 16
#define NARM_EMRD_REG_mrdd 15, 0

#define NARM_EMRD50_ADDR	((unsigned long volatile *)0xff80054C)		/* Ethernet MII Read Data Register */
#define NARM_EMRD20UM_ADDR	((unsigned long volatile *)0xff800430)		/* Ethernet MII Read Data Register */


/* Ethernet MII Indicators Register */

#define NARM_EMIR_REG_reserved 31, 2
#define NARM_EMIR_REG_scan 1, 1
#define NARM_EMIR_REG_busy 0, 0


#define NARM_EMIR20UM_REG_reserved1 31, 4
#define NARM_EMIR20UM_REG_miilf 3, 3
#define NARM_EMIR20UM_REG_nvalid 2, 2
#define NARM_EMIR20UM_REG_scan 1, 1
#define NARM_EMIR20UM_REG_busy 0, 0

#define NARM_EMIR50_ADDR		((unsigned long volatile *)0xff800550)		/* Ethernet MII Indicators Register */
#define NARM_EMIR20UM_ADDR	((unsigned long volatile *)0xff800434)		/* Ethernet MII Indicators Register */



#define NARM_ESTLCR_REG_reserved 31, 3
#define NARM_ESTLCR_REG_autoz 2, 2
#define NARM_ESTLCR_REG_rxen 1, 1
#define NARM_ESTLCR_REG_itxa 0, 0

#define NARM_ESTLCR_ADDR		    ((unsigned long volatile *)0xff800410)	


#define NARM_ESAFR_REG_reserved 31, 4
#define NARM_ESAFR_REG_pro 3, 3
#define NARM_ESAFR_REG_prm 2, 2
#define NARM_ESAFR_REG_pra 1, 1
#define NARM_ESAFR_REG_broad 0, 0

#define NARM_ESAFR_ADDR             ((unsigned long volatile *)0xff8005C0)

#define NARM_EB2BIPGGTR50_ADDR      ((unsigned long volatile *)0xff800440)
#define NARM_ENB2BIPGGTR50_ADDR     ((unsigned long volatile *)0xff800444)
#define NARM_ECWCR50_ADDR           ((unsigned long volatile *)0xff800448)

#define NARM_EFE_TRNG50_ADDR        ((unsigned long volatile *)0xff80046c)

#define NARM_EB2BIPGGTR20UM_ADDR    ((unsigned long volatile *)0xff800408)
#define NARM_ENB2BIPGGTR20UM_ADDR   ((unsigned long volatile *)0xff80040C)
#define NARM_ECWCR20UM_ADDR         ((unsigned long volatile *)0xff800410)

#define NARM_ESA1R50_ADDR           ((unsigned long volatile *)0xff8005C4)
#define NARM_ESA2R50_ADDR           ((unsigned long volatile *)0xff8005C8)
#define NARM_ESA3R50_ADDR           ((unsigned long volatile *)0xff8005CC)

#define NARM_ESA3R20UM_ADDR         ((unsigned long volatile *)0xff800440)
#define NARM_ESA2R20UM_ADDR         ((unsigned long volatile *)0xff800444)
#define NARM_ESA1R20UM_ADDR         ((unsigned long volatile *)0xff800448)

#define NARM_EHT1_ADDR              ((unsigned long volatile *)0xff8005D0)
#define NARM_EHT2_ADDR              ((unsigned long volatile *)0xff8005D4)
#define NARM_EHT3_ADDR              ((unsigned long volatile *)0xff8005D8)
#define NARM_EHT4_ADDR              ((unsigned long volatile *)0xff8005DC)

/* Statistics Counter Register */

#define NARM_ESTATS_REG_reserved 31, 16
#define NARM_ESTATS_REG_cnt 15, 0

#define NARM_ECRCEC_ADDR		((unsigned long volatile *)0xff800580)	
#define NARM_EAEC_ADDR		    ((unsigned long volatile *)0xff800584)	
#define NARM_ECEC_ADDR		    ((unsigned long volatile *)0xff800588)	
#define NARM_ELNGFC_ADDR		((unsigned long volatile *)0xff80058C)	
#define NARM_ESHRTFC_ADDR		((unsigned long volatile *)0xff800590)	
#define NARM_ELCC_ADDR		    ((unsigned long volatile *)0xff800594)	
#define NARM_EEDC_ADDR		    ((unsigned long volatile *)0xff800598)	
#define NARM_EMCC_ADDR		    ((unsigned long volatile *)0xff80059C)		


/* IEEE 1284 Port Control Registers */

#define NARM_PPCR_REG_porte 31, 31
#define NARM_PPCR_REG_dmae 30, 30
#define NARM_PPCR_REG_intep 29, 29
#define NARM_PPCR_REG_intea 28, 28
#define NARM_PPCR_REG_ecp 27, 27
#define NARM_PPCR_REG_loop 26, 26
#define NARM_PPCR_REG_strobe 25, 24
#define NARM_PPCR_REG_man 23, 23
#define NARM_PPCR_REG_fast 22, 22
#define NARM_PPCR_REG_bidir 21, 21
#define NARM_PPCR_REG_pio 20, 20
#define NARM_PPCR_REG_mstb_n 19, 19
#define NARM_PPCR_REG_autofd_n 18, 18
#define NARM_PPCR_REG_init_n 17, 17
#define NARM_PPCR_REG_hsel_n 16, 16
#define NARM_PPCR_REG_reserved1 15, 8
#define NARM_PPCR_REG_ack_n 7, 7
#define NARM_PPCR_REG_fifoe 6, 6
#define NARM_PPCR_REG_obe 5, 5
#define NARM_PPCR_REG_acki 4, 4
#define NARM_PPCR_REG_busy 3, 3
#define NARM_PPCR_REG_pe 2, 2
#define NARM_PPCR_REG_psel 1, 1
#define NARM_PPCR_REG_fault_n 0, 0

#define NARM_PPCR_ADDR_BASE                               (0xffa00010)
#define NARM_PPCR_ADDR(x)		((unsigned long volatile *) (NARM_PPCR_ADDR_BASE + (x << 2)))
#define NARM_PPDR_ADDR_BASE                               (0xffa00020)
#define NARM_PPDR_ADDR(x)		((unsigned long volatile *) (NARM_PPDR_ADDR_BASE + (x << 2)))		

/* Basic structure of the Serial Channel Control Register A */

#define NARM_SCRA_REG_ce 31, 31
#define NARM_SCRA_REG_brk 30, 30
#define NARM_SCRA_REG_stickp 29, 29
#define NARM_SCRA_REG_eps 28, 28
#define NARM_SCRA_REG_pe 27, 27
#define NARM_SCRA_REG_stop 26, 26
#define NARM_SCRA_REG_wls 25, 24
#define NARM_SCRA_REG_ctstx 23, 23
#define NARM_SCRA_REG_rtsrx 22, 22
#define NARM_SCRA_REG_rl 21, 21
#define NARM_SCRA_REG_ll 20, 20
#define NARM_SCRA_REG_out2 19, 19
#define NARM_SCRA_REG_out1 18, 18
#define NARM_SCRA_REG_dtr 17, 17
#define NARM_SCRA_REG_rts 16, 16
#define NARM_SCRA_REG_erxbrk 15, 15
#define NARM_SCRA_REG_erxfe 14, 14
#define NARM_SCRA_REG_erxpe 13, 13
#define NARM_SCRA_REG_erxorun 12, 12
#define NARM_SCRA_REG_erxdrdy 11, 11
#define NARM_SCRA_REG_erxhalf 10, 10

#define NARM_SCRA_REG_erxbc 9, 9
#define NARM_SCRA_REG_erxdma 8, 8
#define NARM_SCRA_REG_erxdcd 7, 7
#define NARM_SCRA_REG_erxri 6, 6
#define NARM_SCRA_REG_erxdsr 5, 5
#define NARM_SCRA_REG_etxcts 4, 4
#define NARM_SCRA_REG_etxobe 3, 3
#define NARM_SCRA_REG_etxhalf 2, 2
#define NARM_SCRA_REG_etxbc 1, 1
#define NARM_SCRA_REG_etxdma 0, 0

#ifdef BSP_ARM9
#define NARM_SC1CRA_ADDR        (unsigned long volatile *)0x90200040
#define NARM_SC1CRB_ADDR        (unsigned long volatile *)0x90200044
#define NARM_SC1SRA_ADDR        (unsigned long volatile *)0x90200048
#define NARM_SC1BRG_ADDR        (unsigned long volatile *)0x9020004C
#define NARM_SC1FIFO_ADDR       (unsigned long volatile *)0x90200050
#define NARM_SC1RBT_ADDR        (unsigned long volatile *)0x90200054
#define NARM_SC1RCT_ADDR        (unsigned long volatile *)0x90200058
#define NARM_SC1RMR_ADDR        (unsigned long volatile *)0x9020005C
#define NARM_SC2CRA_ADDR        (unsigned long volatile *)0x90200000
#define NARM_SC2CRB_ADDR        (unsigned long volatile *)0x90200004
#define NARM_SC2SRA_ADDR        (unsigned long volatile *)0x90200008
#define NARM_SC2BRG_ADDR        (unsigned long volatile *)0x9020000C
#define NARM_SC2FIFO_ADDR       (unsigned long volatile *)0x90200010
#define NARM_SC2RBT_ADDR        (unsigned long volatile *)0x90200014
#define NARM_SC2RCT_ADDR        (unsigned long volatile *)0x90200018
#define NARM_SC2RMR_ADDR        (unsigned long volatile *)0x9020001C

#define NARM_SC3CRA_ADDR        (unsigned long volatile *)0x90300000
#define NARM_SC3CRB_ADDR        (unsigned long volatile *)0x90300004
#define NARM_SC3SRA_ADDR        (unsigned long volatile *)0x90300008
#define NARM_SC3BRG_ADDR        (unsigned long volatile *)0x9030000C
#define NARM_SC3FIFO_ADDR       (unsigned long volatile *)0x90300010
#define NARM_SC3RBT_ADDR        (unsigned long volatile *)0x90300014
#define NARM_SC3RCT_ADDR        (unsigned long volatile *)0x90300018
#define NARM_SC3RMR_ADDR        (unsigned long volatile *)0x9030001C
#define NARM_SC4CRA_ADDR        (unsigned long volatile *)0x90300040
#define NARM_SC4CRB_ADDR        (unsigned long volatile *)0x90300044
#define NARM_SC4SRA_ADDR        (unsigned long volatile *)0x90300048
#define NARM_SC4BRG_ADDR        (unsigned long volatile *)0x9030004C
#define NARM_SC4FIFO_ADDR       (unsigned long volatile *)0x90300050
#define NARM_SC4RBT_ADDR        (unsigned long volatile *)0x90300054
#define NARM_SC4RCT_ADDR        (unsigned long volatile *)0x90300058
#define NARM_SC4RMR_ADDR        (unsigned long volatile *)0x9030005C
#else
#define NARM_SC1CRA_ADDR        (unsigned long volatile *)0xffd00000
#define NARM_SC2CRA_ADDR        (unsigned long volatile *)0xffd00040
#define NARM_SC1CRB_ADDR        (unsigned long volatile *)0xffd00004
#define NARM_SC2CRB_ADDR        (unsigned long volatile *)0xffd00044
#define NARM_SC1SRA_ADDR        (unsigned long volatile *)0xffd00008
#define NARM_SC2SRA_ADDR        (unsigned long volatile *)0xffd00048
#define NARM_SC1BRG_ADDR        (unsigned long volatile *)0xffd0000C
#define NARM_SC2BRG_ADDR        (unsigned long volatile *)0xffd0004C
#define NARM_SC1FIFO_ADDR        (unsigned long volatile *)0xffd00010
#define NARM_SC2FIFO_ADDR        (unsigned long volatile *)0xffd00050
#define NARM_SC1RBT_ADDR        (unsigned long volatile *)0xffd00014
#define NARM_SC2RBT_ADDR        (unsigned long volatile *)0xffd00054
#define NARM_SC1RCT_ADDR        (unsigned long volatile *)0xffd00018
#define NARM_SC2RCT_ADDR        (unsigned long volatile *)0xffd00058
#define NARM_SC1RMR_ADDR        (unsigned long volatile *)0xffd0001C
#define NARM_SC2RMR_ADDR        (unsigned long volatile *)0xffd0005C
#endif

/* structure of the Serial Channel Control Register B */

#define NARM_SCRB_REG_rdm1 31, 31
#define NARM_SCRB_REG_rdm2 30, 30
#define NARM_SCRB_REG_rdm3 29, 29
#define NARM_SCRB_REG_rdm4 28, 28
#define NARM_SCRB_REG_rbgt 27, 27
#define NARM_SCRB_REG_rcgt 26, 26
#define NARM_SCRB_REG_cspol 25, 25
#define NARM_SCRB_REG_reserved_1 24, 22
#define NARM_SCRB_REG_mode 21, 20
#define NARM_SCRB_REG_bitordr 19, 19
#define NARM_SCRB_REG_mam1 18, 18
#define NARM_SCRB_REG_mam2 17, 17
#define NARM_SCRB_REG_reserved_2 16, 0

/* structure of the Serial Channel Control Register C */

#define NARM_SCRC_REG_nflag 31, 28
#define NARM_SCRC_REG_reserved_1 27, 24
#define NARM_SCRC_REG_crc 23, 22
#define NARM_SCRC_REG_rxcrc 21, 21
#define NARM_SCRC_REG_chkcrc 20, 20
#define NARM_SCRC_REG_reserved_2 19, 18
#define NARM_SCRC_REG_txcrc 17, 17
#define NARM_SCRC_REG_flg_idl 16, 16
#define NARM_SCRC_REG_reserved_3 15, 0

/* structure of the Serial Channel Bit-Rate Generator Reg */

#define NARM_SBRG_REG_ebit 31, 31
#define NARM_SBRG_REG_tmode 30, 30
#define NARM_SBRG_REG_rxsrc 29, 29
#define NARM_SBRG_REG_txsrc 28, 28
#define NARM_SBRG_REG_rxext 27, 27
#define NARM_SBRG_REG_txext 26, 26
#define NARM_SBRG_REG_clkmux 25, 24
#define NARM_SBRG_REG_txcinv 23, 23
#define NARM_SBRG_REG_rxcinv 22, 22
#ifdef BSP_ARM9
#define NARM_SBRG_REG_spcpol 21, 21
#define NARM_SBRG_REG_tcdr 20, 19
#define NARM_SBRG_REG_rcdr 18, 17
#define NARM_SBRG_REG_tics 16, 16
#define NARM_SBRG_REG_rics 15, 15
#define NARM_SBRG_REG_nreg 14, 0
#else
#define NARM_SBRG_REG_clkinv 21, 21
#define NARM_SBRG_REG_tcdr 20, 19
#define NARM_SBRG_REG_reserved2
#define NARM_SBRG_REG_rcdr 17, 16
#define NARM_SBRG_REG_reserved3 15, 15
#define NARM_SBRG_REG_tics 14, 14
#define NARM_SBRG_REG_reserved4 13, 13
#define NARM_SBRG_REG_rics 12, 12
#define NARM_SBRG_REG_reserved5 11, 11
#define NARM_SBRG_REG_nreg 10, 0
#endif

/* structure of the Serial Channel Status Register B */

#define NARM_SSRB_REG_flags 31, 31
#define NARM_SSRB_REG_idle 30, 30
#define NARM_SSRB_REG_reserved_1 29, 26
#define NARM_SSRB_REG_rxbcam1 25, 25
#define NARM_SSRB_REG_rxbcam2 24, 24
#define NARM_SSRB_REG_rxbcam3 23, 23
#define NARM_SSRB_REG_rxbcam4 22, 22
#define NARM_SSRB_REG_rxbcn 21, 21
#define NARM_SSRB_REG_rxbcc 20, 20
#define NARM_SSRB_REG_rxbco 19, 19
#define NARM_SSRB_REG_rxbca 18, 18
#define NARM_SSRB_REG_rxbcl 17, 17
#define NARM_SSRB_REG_rxbcab 16, 16
#define NARM_SSRB_REG_txbcc 15, 15
#define NARM_SSRB_REG_txbcu 14, 14
#define NARM_SSRB_REG_reserved_2 13, 0

/* structure of the Serial Channel Receive Buffer Timer Reg */

#define NARM_SRBT_REG_trun 31, 31
#define NARM_SRBT_REG_reserved 30, 15
#define NARM_SRBT_REG_bt 14, 0

/* structure of the Serial Channel Status Register A*/

#define NARM_SSRA_REG_match1 31, 31
#define NARM_SSRA_REG_match2 30, 30
#define NARM_SSRA_REG_match3 29, 29
#define NARM_SSRA_REG_match4 28, 28
#define NARM_SSRA_REG_bgap 27, 27
#define NARM_SSRA_REG_cgap 26, 26
#define NARM_SSRA_REG_reserved 25, 22
#define NARM_SSRA_REG_rxfdb 21, 20
#define NARM_SSRA_REG_dcd 19, 19
#define NARM_SSRA_REG_ri 18, 18
#define NARM_SSRA_REG_dsr 17, 17
#define NARM_SSRA_REG_cts 16, 16
#define NARM_SSRA_REG_rxbrk 15, 15
#define NARM_SSRA_REG_rxfe 14, 14
#define NARM_SSRA_REG_rxpe 13, 13
#define NARM_SSRA_REG_rxover 12, 12
#define NARM_SSRA_REG_rxrdy 11, 11
#define NARM_SSRA_REG_rxhalf 10, 10
#define NARM_SSRA_REG_rxbc 9, 9
#define NARM_SSRA_REG_rxfull 8, 8
#define NARM_SSRA_REG_rxdcdi 7, 7
#define NARM_SSRA_REG_rxrii 6, 6
#define NARM_SSRA_REG_rxdsri 5, 5
#define NARM_SSRA_REG_txctsi 4, 4
#define NARM_SSRA_REG_txrdy 3, 3
#define NARM_SSRA_REG_txhalf 2, 2
#define NARM_SSRA_REG_txbc 1, 1
#define NARM_SSRA_REG_txempty 0, 0


#ifdef __cplusplus
}
#endif


#endif
