diff --git a/kernel-patches/include/asm-armnommu/arch-netarm/netarm_config.h b/kernel-patches/include/asm-armnommu/arch-netarm/netarm_config.h
index 42341a2..7937237 100644
--- a/kernel-patches/include/asm-armnommu/arch-netarm/netarm_config.h
+++ b/kernel-patches/include/asm-armnommu/arch-netarm/netarm_config.h
@@ -10,10 +10,12 @@
  *         This include file has to be included first so dependency
  *         to linux/autoconf.h is created. Otherwise it would be
  *         ignored by mkdep
- *  
+ *
  ********************************************************************** */
 /*********************************************************************** *
  *  @History:
+ *     2010/07/07 : Set 1 wait state to SDRAM because of problems at high
+ *                  temperatures (over 70ºC). (Hector Palacios)
  *     2003/12/09 : added DIGI_ME support
  *     2003/11/26 : added CS4
  *     2003/10/16 : added CONFIG_FS_MODULE_DIGI
@@ -29,14 +31,14 @@
  *                  predefining a dummy baud rate that is overwritten by kernel
  *                  driver later
  *     2003/01/29 : fixed eeprom GPIOS for UNC20
- *                  fixed serial configuration for UNC20 
+ *                  fixed serial configuration for UNC20
  *                  added disabling of serial channels
  *                  ttyS0 is for first serial channel provided by driver
  *     2002/11/28 : added CONFIG_FS_SERIAL_DISABLE_HANDSHAKE
  *     2002/11/06 : added ModNET20 support
  *     2002/10/23 : BugID 73: Port C4 wrong initialised
  *                  added NetRadio
- *                  define FS_PARAM_EEPROM_USE_C5 and C6   
+ *                  define FS_PARAM_EEPROM_USE_C5 and C6
  *********************************************************************** */
 
 #ifndef NETARM_CONFIG_H
@@ -52,7 +54,7 @@
 #if defined(CONFIG_FS_MODULE_MODNET50)
 # define FS_PARAM_NETARM_50
 # define FS_PARAM_BOARD_HAS_CS2
-# define FS_PARAM_BOARD_HAS_CS3 
+# define FS_PARAM_BOARD_HAS_CS3
 # define FS_PARAM_BOARD_HAS_CS4
 #elif defined(CONFIG_FS_MODULE_UNC20)
 # define FS_PARAM_NETARM_20UM
@@ -264,7 +266,7 @@ extern int nNetarmCrystalFreq; // arch.c
 
 // input from EEPROM is C5 or C6
 #if defined(CONFIG_FS_MODULE_MODNET50)
-# define FS_PARAM_FLASH_BASE_RESCUE_KERNEL  (0x02600000) // 8 MB module 
+# define FS_PARAM_FLASH_BASE_RESCUE_KERNEL  (0x02600000) // 8 MB module
 # define FS_PARAM_EEPROM_FLASH_BASE_OFFSET  (0x007F0000) // 8 MB module
 # ifdef CONFIG_FS_MODULE_REV_0
 #  define FS_PARAM_EEPROM_USE_C5
@@ -276,7 +278,7 @@ extern int nNetarmCrystalFreq; // arch.c
 # define FS_PARAM_EEPROM_USE_C6
 # define FS_PARAM_EEPROM_USE_C7_OUTPUT
 #elif defined(CONFIG_FS_MODULE_UNC20)
-# define FS_PARAM_FLASH_BASE_RESCUE_KERNEL  (0x02600000) // 8 MB module 
+# define FS_PARAM_FLASH_BASE_RESCUE_KERNEL  (0x02600000) // 8 MB module
 # define FS_PARAM_EEPROM_FLASH_BASE_OFFSET  (0x007F0000) // 8 MB module
 # define FS_PARAM_EEPROM_USE_C6
 # define FS_PARAM_EEPROM_USE_C2_OUTPUT
@@ -288,7 +290,7 @@ extern int nNetarmCrystalFreq; // arch.c
 	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) |	\
         NETARM_MEM_OPT_BCYC_2 |			\
 	NETARM_MEM_OPT_BSIZE_16 | 		\
-	NETARM_MEM_OPT_WAIT_STATES(0) | 		\
+	NETARM_MEM_OPT_WAIT_STATES(1) |		\
 	NETARM_MEM_OPT_16BIT | 			\
 	NETARM_MEM_OPT_READ_ASYNC | 		\
 	NETARM_MEM_OPT_WRITE_ASYNC
diff --git a/kernel-patches/include/asm-armnommu/arch-netarm/netarm_mem_module.h b/kernel-patches/include/asm-armnommu/arch-netarm/netarm_mem_module.h
new file mode 100644
index 0000000..0fd1ef4
--- /dev/null
+++ b/kernel-patches/include/asm-armnommu/arch-netarm/netarm_mem_module.h
@@ -0,0 +1,200 @@
+/*
+ * include/asm-armnommu/arch-netarm/netarm_mem_module.h
+ *
+ * Copyright (C) 2000, 2001 NETsilicon, Inc.
+ * Copyright (C) 2000, 2001 Red Hat, Inc.
+ *
+ * This software is copyrighted by Red Hat. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall Red Hat
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ */
+/***********************************************************************
+ *
+ *  Copyright 2002,2003 by FS Forth-Systeme GmbH.
+ *  All rights reserved.
+ *
+ *  Ported to ModNET and Kernel 2.4.20 by Markus Pietrek.
+ *
+ ********************************************************************** */
+/*********************************************************************** *
+ *  @History:
+ *     2010/07/07 : reduce SDRAM refresh cycle because of problems at
+ *                  high temperatures (over 70ºC). (Hector Palacios)
+ *     2003/04/03 : fixed UNC20 CS configuration
+ *     2003/01/23 : copied from LxNET50-2.0 2.4.17 to 2.4.20
+ *     2002/11/06 : added OPTIONS_B
+ *********************************************************************** */
+
+#ifndef __NETARM_MEM_MODULE_REGISTERS_H
+#define __NETARM_MEM_MODULE_REGISTERS_H
+
+/* GEN unit register offsets */
+
+#define	NETARM_MEM_MODULE_BASE		(0xFFC00000)
+
+#define	NETARM_MEM_MODULE_CONFIG	(0x00)
+#define	NETARM_MEM_CS0_BASE_ADDR	(0x10)
+#define	NETARM_MEM_CS0_OPTIONS		(0x14)
+#define	NETARM_MEM_CS0_OPTIONS_B	(0x18)
+#define	NETARM_MEM_CS1_BASE_ADDR	(0x20)
+#define	NETARM_MEM_CS1_OPTIONS		(0x24)
+#define	NETARM_MEM_CS1_OPTIONS_B	(0x28)
+#define	NETARM_MEM_CS2_BASE_ADDR	(0x30)
+#define	NETARM_MEM_CS2_OPTIONS		(0x34)
+#define	NETARM_MEM_CS2_OPTIONS_B	(0x38)
+#define	NETARM_MEM_CS3_BASE_ADDR	(0x40)
+#define	NETARM_MEM_CS3_OPTIONS		(0x44)
+#define	NETARM_MEM_CS3_OPTIONS_B	(0x48)
+#define	NETARM_MEM_CS4_BASE_ADDR	(0x50)
+#define	NETARM_MEM_CS4_OPTIONS		(0x54)
+#define	NETARM_MEM_CS4_OPTIONS_B	(0x58)
+
+/* select bitfield defintions */
+
+/* Module Configuration Register ( 0xFFC0_0000 ) */
+
+#define NETARM_MEM_CFG_REFR_COUNT_MASK	(0xFF000000)
+#define NETARM_MEM_CFG_REFRESH_EN	(0x00800000)
+
+#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS	(0x00000000)
+#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS	(0x00200000)
+#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS	(0x00400000)
+#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS	(0x00600000)
+
+#define NETARM_MEM_CFG_PORTC_AMUX	(0x00100000)
+
+#define NETARM_MEM_CFG_A27_ADDR		(0x00080000)
+#define NETARM_MEM_CFG_A27_CS0OE	(0x00000000)
+
+#define NETARM_MEM_CFG_A26_ADDR		(0x00040000)
+#define NETARM_MEM_CFG_A26_CS0WE	(0x00000000)
+
+#define NETARM_MEM_CFG_A25_ADDR		(0x00020000)
+#define NETARM_MEM_CFG_A25_BLAST	(0x00000000)
+
+#define NETARM_MEM_CFG_PORTC_AMUX2	(0x00010000)
+
+
+/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
+/* the expression will round down, so make sure to reverse it to verify */
+/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
+/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
+
+#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
+					 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
+					    ) - (1) ) << (24)))
+#ifndef FS_PARAM_NETARM_20UM
+# define FS_PARAM_REFRESH_PERIOD (NETARM_MEM_REFR_PERIOD_USEC(16))
+#else
+# define FS_PARAM_REFRESH_PERIOD 0x0d000000 // NETARM_MEM_REFR_PERIOD_USEC is not
+                                            // precise enough to get this value
+                                            // for 55 MHz
+#endif
+
+#if 0
+/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
+/* the expression will round down, so make sure to reverse it toverify */
+/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
+
+#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
+					 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
+					    ) - (1) ) << (24)))
+#endif
+
+/* Base Address Registers (0xFFC0_00X0) */
+
+#define NETARM_MEM_BAR_BASE_MASK	(0xFFFFF000)
+
+/* macro to define base */
+
+#define NETARM_MEM_BAR_BASE(x)		((x) & NETARM_MEM_BAR_BASE_MASK)
+
+#define NETARM_MEM_BAR_DRAM_FP		(0x00000000)
+#define NETARM_MEM_BAR_DRAM_EDO		(0x00000100)
+#define NETARM_MEM_BAR_DRAM_SYNC	(0x00000200)
+
+#define NETARM_MEM_BAR_DRAM_MUX_INT	(0x00000000)
+#define NETARM_MEM_BAR_DRAM_MUX_EXT	(0x00000080)
+
+#define NETARM_MEM_BAR_DRAM_MUX_BAL	(0x00000000)
+#define NETARM_MEM_BAR_DRAM_MUX_UNBAL	(0x00000020)
+
+#define NETARM_MEM_BAR_1BCLK_IDLE	(0x00000010)
+
+#define NETARM_MEM_BAR_DRAM_SEL		(0x00000008)
+
+#define NETARM_MEM_BAR_BURST_EN		(0x00000004)
+
+#define NETARM_MEM_BAR_WRT_PROT		(0x00000002)
+
+#define NETARM_MEM_BAR_VALID		(0x00000001)
+
+/* Option Registers (0xFFC0_00X4) */
+
+/* macro to define which bits of the base are significant */
+
+#define NETARM_MEM_OPT_BASE_USE(x)	((x) & NETARM_MEM_BAR_BASE_MASK)
+
+#define NETARM_MEM_OPT_WAIT_MASK	(0x00000F00)
+
+#define	NETARM_MEM_OPT_WAIT_STATES(x)	(((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
+
+#define NETARM_MEM_OPT_BCYC_1		(0x00000000)
+#define NETARM_MEM_OPT_BCYC_2		(0x00000040)
+#define NETARM_MEM_OPT_BCYC_3		(0x00000080)
+#define NETARM_MEM_OPT_BCYC_4		(0x000000C0)
+
+#define NETARM_MEM_OPT_BSIZE_2		(0x00000000)
+#define NETARM_MEM_OPT_BSIZE_4		(0x00000010)
+#define NETARM_MEM_OPT_BSIZE_8		(0x00000020)
+#define NETARM_MEM_OPT_BSIZE_16		(0x00000030)
+
+#define NETARM_MEM_OPT_32BIT		(0x00000000)
+#define NETARM_MEM_OPT_16BIT		(0x00000004)
+#define NETARM_MEM_OPT_8BIT		(0x00000008)
+#define NETARM_MEM_OPT_32BIT_EXT_ACK	(0x0000000C)
+
+#define NETARM_MEM_OPT_BUS_SIZE_MASK	(0x0000000C)
+
+#define NETARM_MEM_OPT_READ_ASYNC	(0x00000000)
+#define NETARM_MEM_OPT_READ_SYNC	(0x00000002)
+
+#define NETARM_MEM_OPT_WRITE_ASYNC	(0x00000000)
+#define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
+
+/* Option B Registers (0xFFC0_00x8) */
+
+#define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
+#define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
+#define NETARM_MEM_OPTB_BCYC_PLUS0   	(0x00000000)
+#define NETARM_MEM_OPTB_BCYC_PLUS4   	(0x00000004)
+#define NETARM_MEM_OPTB_BCYC_PLUS8   	(0x00000008)
+#define NETARM_MEM_OPTB_BCYC_PLUS12  	(0x0000000C)
+
+#define NETARM_MEM_OPTB_WAIT_PLUS0   	(0x00000000)
+#define NETARM_MEM_OPTB_WAIT_PLUS16   	(0x00000010)
+#define NETARM_MEM_OPTB_WAIT_PLUS32   	(0x00000020)
+#define NETARM_MEM_OPTB_WAIT_PLUS48   	(0x00000030)
+
+#endif
+