/*
 *            Copyright (c) 1998-2000 by NETsilicon Inc.
 *
 *  This software is copyrighted by and is the sole property of 
 *  NETsilicon.  All rights, title, ownership, or other interests
 *  in the software remain the property of NETsilicon.  This
 *  software may only be used in accordance with the corresponding
 *  license agreement.  Any unauthorized use, duplication, transmission,  
 *  distribution, or disclosure of this software is expressly forbidden.
 *
 *  This Copyright notice may not be removed or modified without prior
 *  written consent of NETsilicon.
 *
 *  NETsilicon, reserves the right to modify this software
 *  without notice.
 *
 *  NETsilicon
 *  411 Waverley Oaks Road                  USA 781.647.1234
 *  Suite 227                               http://www.netsilicon.com
 *  Waltham, MA 02452                       AmericaSales@netsilicon.com
 *
 *************************************************************************
 *
 *     Module Name: serlDev.h
 *         Version: 1.00
 *   Original Date: 07/09/2001	
 *          Author: Naum Gurevich
 *        Language: Ansi C
 * Compile Options: 
 * Compile defines: 
 *       Libraries: 
 *    Link Options: 
 *
 *    Entry Points: 
 *
 * Description.
 * =======================================================================
 * This header file contains declarations for the SPI device.
 *                                                                        
 *                                                                        
 * Edit Date/Ver   Edit Description
 * ==============  ===================================================
 *
 *
 */

#ifndef spiDev_h
#define spiDev_h
#ifdef __cplusplus
extern "C"
{
#endif
#define   COM1             "/com/0"
#define   COM2             "/com/1"

/**
 * SPI command codes for ioctl.
 *
 * @external
 * @category SPI
 * @since 6.0
 * @name spi_command       "SPI ioctls"
 *
 * @param SIO_GET_REG           Read the XICOR's control register
 * @param SIO_SET_REG           Write to the XICOR's control register
 * @param SIO_SLAVE_GET         Get master / slave mode of SPI driver
 *                              <list type="unordered">
 *                                  <item>Master = 0</item>
 *                                  <item>Slave = 1</item>
 *                              </list>
 * @param SIO_RD_ADDRESS_SET    Set EEPROM address for next read:
 *                              <list type="unordered">
 *                                  <item>Master mode: 1-32767</item>
 *                                  <item>Master mode with XICOR: 1-256</item>
 *                                  <item>Slave mode: 1-32767</item>
 *                                  <item>Slave mode and select ISR: 40-32767</item>
 *                              </list>
 *                              The address is automatically increased after each 
 *                              operation by the number of bytes actually read
 * @param SIO_RD_ADDRESS_GET    Get EEPROM address for next read:
 *                              <list type="unordered">
 *                                  <item>Master mode: 1-32767</item>
 *                                  <item>Master mode with XICOR: 1-256</item>
 *                                  <item>Slave mode: 1-32767</item>
 *                                  <item>Slave mode and select ISR: 40-32767</item>
 *                              </list>
 * @param SIO_WR_ADDRESS_SET    Set EEPROM address for next write
 *                              <list type="unordered">
 *                                  <item>Master mode: 1-32767</item>
 *                                  <item>Master mode with XICOR: 1-256</item>
 *                                  <item>Slave mode: 1-32767</item>
 *                                  <item>Slave mode and select ISR: 40-32767</item>
 *                              </list>
 * @param SIO_WR_ADDRESS_GET    Get EEPROM address for next write
 *                              <list type="unordered">
 *                                  <item>Master mode: 1-32767</item>
 *                                  <item>Master mode with XICOR: 1-256</item>
 *                                  <item>Slave mode: 1-32767</item>
 *                                  <item>Slave mode and select ISR: 40-32767</item>
 *                              </list>
 * @param SIO_SPI_HW_SET        Set hardware option for the SPI operation:
 *                              <list type="unordered">
 *                                  <item>SIO_SPI_Direct</item>
 *                                  <item>SIO_SPI_X250200</item>
 *                              </list>
 * @param SIO_SPI_HW_GET        Get hardware option for the SPI operation
 *                              <list type="unordered">
 *                                  <item>SIO_SPI_Direct</item>
 *                                  <item>SIO_SPI_X250200</item>
 *                              </list>
 * @param SIO_SPI_SS_SET        Set port for generating "Slave Select" signal:
 *                              <list type="unordered">
 *                                  <item>Bits 15-8: registry number</item>
 *                                  <item>Bits 7-0: bit number</item>
 *                              </list>
 * @param SIO_SPI_USE_SEL_ISR   Use interrupt on the SEL signal
 * @param SIO_SET_SLAVE_TIMEOUT Set time out value for the SPI slave mode in ticks
 * @param SIO_GET_SLAVE_TIMEOUT Get time out value for the SPI slave mode in ticks
 * @param SIO_SET_SA_SIGNAL     Generate an additional signal when slave is ready to accept CLK signals
 * @param SIO_SET_TXCINV        set TXD to be driven on rising edge of TX clock
 *                              <list type="unordered">
 *                                  <item>0 = high-to-low transition</item>
 *                                  <item>1 = low-to-high transition</item>
 *                              </list>
 * @param SIO_SET_RXCINV        set RRXD to be sampled on falling edge of RX clock
 *                              <list type="unordered">
 *                                  <item>0 = high-to-low transition</item>
 *                                  <item>1 = low-to-high transition</item>
 *                              </list>
 * @param SIO_SET_SPI_CLOCK_HI  Set initial value of the clock signal High
 * @param SIO_GET_LSB           Get the bit order configuration for how bits
 *                              are transmitted and received
 *                              <list type="unordered">
 *                                  <item>0 = Bits are processed MSB first, LSB last</item>
 *                                  <item>1 = Bits are processed LSB first, MSB last</item>
 *                              </list>
 * @param SIO_SET_LSB           Set the bit order configuration for how bits
 *                              are transmitted and received
 *                              <list type="unordered">
 *                                  <item>0 = Bits are processed MSB first, LSB last</item>
 *                                  <item>1 = Bits are processed LSB first, MSB last</item>
 *                              </list>
 * @obsolete 6.0c
 * SIO_GET_REG
 * SIO_SET_REG
 * SIO_RD_ADDRESS_SET
 * SIO_RD_ADDRESS_GET
 * SIO_WR_ADDRESS_SET
 * SIO_WR_ADDRESS_GET
 * SIO_SPI_HW_SET
 * SIO_SPI_HW_GET
 */

#define SIO_GET_REG             (0x100A)	/* Get EEEPROM'S register */
#define SIO_SET_REG             (0x100B)	/* Set EEEPROM'S register */
#define SIO_SLAVE_GET           (0X100C)   /* Get master / slave mode of SPI driver */
#define SIO_RD_ADDRESS_SET      (0X100D)    /* Set read address for EEPROM  */
#define SIO_RD_ADDRESS_GET      (0X100E)    /* Get read address for EEPROM  */
#define SIO_WR_ADDRESS_SET      (0X100F)    /* Set write address for EEPROM */
#define SIO_WR_ADDRESS_GET      (0X1010)    /* Get write address for EEPROM */
#define SIO_SPI_HW_SET          (0x1013)	/* Set hardware option for the SPI operation */
#define SIO_SPI_HW_GET          (0x1014)	/* Get hardware option for the SPI operation  Currently includes direct connect and XICOR X25020 */
#define SIO_SPI_SS_SET          (0x1015)    /* Set port for generating "Slave Select" signal */
#define SIO_SPI_USE_SEL_ISR     (0x1016)
#define SIO_SET_SLAVE_TIMEOUT   (0x1017)  /* Set time out value for the SPI slave mode */
#define SIO_GET_SLAVE_TIMEOUT   (0x1018)  /* Get time out value for the SPI slave mode */
#define SIO_SET_SA_SIGNAL       (0X1019)  /* Generate an additional signal when slave is ready to accept CLK signals. */
#define SIO_SET_TXCINV          (0x101A) /* set TXD to be driven on rising edge of TX clock  */
#define SIO_SET_RXCINV          (0x101B)  /* set RRXD to be sampled on falling edge of RX clock */
#define SIO_SET_SPI_CLOCK_HI    (0x101C)  /* Set initial value of the clock signal High */
#define SIO_SET_LSB             (0x1044)    /* Set LSB bit ordering */
#define SIO_GET_LSB             (0x1045)    /* Get bit ordering */

/**
 * Option codes for SIO_SPI_HW_SET and SIO_SPI_HW_GET.
 *
 *
 * @external
 * @category SPI
 * @since 6.0
 * @name spiHwOptions       "SPI H/W Options"
 *
 * @param SIO_SPI_DIRECT        Direct connection
 * @param SIO_SPI_X25020        XICOR X250200 EEPROM chip
 * @param SIO_SPI_X25C640U      FAIRCHILD FM25C640U EEPROM chip
 */ 
#define SIO_SPI_DIRECT      (0x1)  /* Direct connections */
#define SIO_SPI_X25020      (0x2)  /* XICOR X250200 EEPROM chip */
#define SIO_SPI_X25C640U    (0x3)  /* FAIRCHILD FM25C640U EEPROM chip */ 

    
/* dev driver call back function prototypes */
extern int netos_spienter (int channel);
extern int netos_spiinit (int channel);
extern int netos_spiopen (int channel, unsigned flags);
extern int netos_spiclose (int channel);
extern int netos_spiread (int channel, void * buffer, int length, int *bytesRead);
extern int netos_spiwrite (int channel, void * buffer, int length, int *bytesWritten);
extern int netos_spiioctl (int channel, int request, char *args);

#ifdef __cplusplus
}
#endif

#endif

