
/*
 Copyright 1999 by Digi International (www.digi.com)

 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 
 implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
 PURPOSE.  See the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
 *	$Id: hou2.h,v 1.24 1999/09/27 18:53:56 chrisel Exp $
 *
 *	This file defines the general purpose ports on the
 *	houston-2 board.
 *
 */
#ifndef _HOU2_H
#define	_HOU2_H

#include "pci_ids.h"		/* gpp4 ADAPTER_ values. */

/*
 *	A 16 bit register which is aligned on a 32 bit boundary
 */
typedef struct u16a32
{
	uint16	reg;
	uint16	unused;
} U16A32;

/*
 *	A 16 bit register which is aligned on a 64 bit boundary
 */
typedef struct u16a64
{
	uint16	reg;
	uint16	unused1;
	uint32	unused2;
} U16A64;

/*
 *	A 16 bit register which is aligned on a 128 bit boundary
 */
typedef struct u16a128
{
	uint16	reg;
	uint16	unused1;
	uint32	unused2[3];
} U16A128;

/*
 *	Here are all the 16 bit registers which are accessed by CSBOOT (host)
 *	or CS1 (board).
 *
 *	One of these structures is always located at offset DSPGPP1_OFFSET
 *	from the base address of CSBOOT or CS1.  If a DSP daughtercard is
 *	installed, a second copy of this structure is located at
 *	DSPGPP2_OFFSET from the base address of CSBOOT or CS1.
 *
 *	You can get the *_OFFSET values from hou2mmap.h.
 */
typedef struct dspgpp
{
	/*
	 *	IDMA data registers.
	 */
	U16A128	idma[30];

	U16A128	unused1[2];

	/*
	 *	IDMAA registers
	 */
	U16A128	idmaa[30];

	U16A128	unused2[2];

	/*
	 *	DSP "UNRESET" bits for DSPs 0-29, plus a couple bits.
	 *	Bit 0 is DSP 0.  0 means DSP is reset.
	 */
	uint32	dspreset ;				/* Offset 400 */

	/*
	 *	DSP power down ACK for DSPs 0-29, plus a couple bits.
	 *	Bit 0 is DSP 0.  0 means DSP is powered down.
	 */
	uint32	dsppwd ;				/* Offset 404 */

	/*
	 *	Misc status
	 *
	 *	WrWr rrrr WrWW rrrr
	 */
	uint16	gpp3;						/* Offset 408 */
		#define	GPP3_BOARD_REV(x)	((x) & 0xf)

		#define	GPP3_MVIP_MASTER	(1<<4)
		#define	GPP3_ENABLE_PCI_INT	(1<<4)	/* London/Chaska */

		#define	GPP3_COMAS_A		(1<<5)
		#define	GPP3_ENABLE_RING_INT	(1<<5)	/* Chaska */

		#define	GPP3_LID_A		(1<<6)
		#define	GPP3_LID_A_T1		(0<<6)
		#define	GPP3_LID_A_E1		(1<<6)

		#define	GPP3_FPGA_REV(x)	(((x) & (0xf<<8)) >> 8)

		#define	GPP3_NO_DAUGHTER	(1<<12)

		#define	GPP3_COMAS_B		(1<<13)

		#define	GPP3_LID_B		(1<<14)
		#define	GPP3_LID_B_T1		(0<<14)
		#define	GPP3_LID_B_E1		(1<<14)

		#define GPP3_T8100_0	(1<<7)			/* Campinas */
		#define GPP3_T8100_1	(1<<15)

		/* houston daughter card */
		#define GPP3_DAU_BRDREV		((x) & 0x0f)
		#define	GPP3_DAU_FREV		(((x) & 0x0f00) >> 8)
		#define GPP3_DAU_PORTNUM	(1<<15)

	/*
	 *	Board ID, processor reset, and LEDs
	 *
	 *	W__W WWWW rrrr rrrr
	 */
	uint16	gpp4;						/* offset 40A */
		#define	GPP4_ADAPTER_ID(x)	((x)&0xff)
		#define GPP4_ADAPTER_BASEID(x)	((x)&0xf1)
		#define GPP4_DAATYPE(x)		(((x)>>1)&7)

		#define	GPP4_O6			(1<<8)
		#define	GPP4_GREEN_A		(1<<9)
		#define	GPP4_YELLOW_A		(1<<10)
		#define	GPP4_GREEN_B		(1<<11)
		#define	GPP4_YELLOW_B		(1<<12)
		#define	GPP4_4640_RESET		(1<<15)

	/*
	 *	Interrupt cause
	 */
	uint16	icause ;				/* offset 40C */
		#define	INT_64011	(1)		/* Galileo 64011 */
		#define	INT_9710	(1 << 1)	/* HiFN 9710 */
		#define	INT_RING	(1 << 1)	/* Chaska ring detect */
		#define	INT_7630	(1 << 2)	/* Lucent 7630 */
		#define	INT_7121_0	(1 << 3) 	/* Lucent 7121 chan 0 */
		#define	INT_MEZZ	(1 << 4)	/* Mezzanine card */
		#define	INT_360_0	(1 << 5)	/* Level 1 360 chan 0 */
		#define	INT_360_1	(1 << 6)	/* Level 1 360 chan 1 */
		#define	INT_4000	(1 << 7)	/* VLSI SC4K MVIP i/f */
		#define INT_HSSWITCH	(1 << 10)	/* Campinas HotSwap Ejector Switch */

		/*
		 * Macro for the LXT360 serial interface busy
		 * indicator. This is set while the FPGA is
		 * clocking data to/from the specified chip.
		 *
		 * Not real smart about being called with a bogus
		 * argument, but we're supposed to be highly
		 * trained professionals.
		 */
		#define	LXT360_BUSY(x)	((1 << 8) << (x))

	/*
	 *	LXT360 serial interface
	 */
	uint16	lxt360[2];				/* offset 40E & 410 */
		#define LXT360_READ	0x0001

	/*
	 * Interrupt mask register (cleared on reset)
	 *
	 * Bit must be set before corresponding device can interrupt
	 * the 4640. Bit postions defined for icause (above) apply.
	 */
	uint16	imask ;					/* offset 412 */

	/*
	 * For CompactPCI Houston, Geographic Address, Hot Swap Control & Status
	 */
	uint16	ga;						/* offset 414 */
		#define GPP_GA(x)	( (x >> 8) & 0x1f)		/* Geo Address */
		#define HS_EIM			(1 << 1)	/* ENUM INT mask */
		#define HS_LOO			(1 << 3)	/* BLUE LED on/off */
		#define HS_EXT			(1 << 6)	/* writing 1 clears EXT */
		#define HS_INS			(1 << 7)	/* writing 1 clears INS */
		#define HS_ENUM			(1 << 13)	/* ENUM state on backplane */
		#define HS_FORCE_ENUM	(1 << 15)	/* writing 1 forces ENUM driven */

	/*
 	 * scratch pad register on compact PCI
	 */
	uint16 scratch ;					/* offset 416 */

	/*
	 * h100 Clock control register on cPCI
	 */
	uint16 H110Clks ;					/* offset 418 */
		#define GPP_NETREF(x) ((x)&0x0c)
		#define GPP_HMASTER(x) ((x)&0x03)

} DSPGPP;

#endif
