
/*
 Copyright 1999 by Digi International (www.digi.com)

 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 
 implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
 PURPOSE.  See the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#if !RAP0
#warning
#warning This file is deprecated:
#warning use triglbl.h instead
#warning
#endif
/*
 *	$Id: global.h,v 1.8 1999/09/03 15:27:18 dickl Exp $
 *
 *	Herein we describe the three possible global structures
 *	pointed to by the global data pointer located at offset
 *	GLOBAL_DATA_OFFSET (currently: 0x1000, but please do use
 *	the #define from the appropriate *mmap.h as this is subject
 *	to change).
 *
 *	By decree, all three of the structures will have a common
 *	structure at the beginning which drivers can use to determine
 *	what code is currently running, and what its status is.
 *	After that, the program that is running is free to define
 *	any additional data it wants to expose to the driver.
 *
 *	The user must supply a few scalar typedef's to use these structures:
 *
 *	host_*		values that are written by the host, read by board
 *	board_*		values that are written by the board, read by host.
 *	shared_*	values that can be read and written by either.
 *	pad_*		padding, not used.
 *
 *	These typedef's are for the purpose of suggesting and/or
 *	enforcing the usage of each member (depending on the compiler).
 *	Items that are of type shared_* must always be written using
 *	uncached accesses.
 *
 *	Suggested typedefs for i386 host's are:
 *		typedef volatile const ulong	board_uint32;
 *		typedef ulong			host_uint32;
 *		typedef volatile ulong		shared_uint32;
 *		typedef ulong			pad_32;
 *	Suggested typedefs for 4640 board processors are:
 *		typedef ulong			board_uint32;
 *		typedef volatile const ulong	host_uint32;
 *		typedef volatile ulong		shared_uint32;
 *		typedef ulong			pad_32;
 *
 *	Endianess is not indicated by these types.  Endianess for
 *	all these types is currently dictated to be little-endian.
 *	For the BOOT and the POST, the endianess must be fixed, since
 *	they do not know the endianess of the host yet.  For the current
 *	FEP, the endianess is also fixed to be little endian.  But the
 *	FEP allows for future *runtime* adjustment of the endianess
 *	of these types (using C++ classes instead of the plain typedefs
 *	suggested above).
 *
 *	A three phase boot scheme is used.  See specs.
 *
 *
 *	NOTE: Somewhat related to these structures are the structures
 *	used only for *debugging purposes*.  These include the debugger
 *	queues, temp counters, temp flags, printf buffers for firmware not
 *	yet to the point that it can communicate thru channel structures,
 *	and statistical program counter sampling.  You can find these
 *	structures in header file "debugcomm.h".
 */
#ifndef _GLOBAL_H
#define _GLOBAL_H

/*
 *	A macro to make 4 byte magic numbers from cute character strings
 */
#define	MKMAGIC(A,B,C,D)	(A + (B<<8) + (C<<16) + (D<<24))

/*
 *	The new read/write structure
 *
 *	This structure is cacheline-32 safe *only* if the firmware always
 *	uses uncached accesses to clear the shared rw_req member.
 */
typedef struct rwdata
{
	/*
	 *	This is the request type
	 */
	shared_uint32	rw_req;
			#define RW_IDLE	 0	/* Idle */
			#define	RW_READ	 1	/* Read request */
			#define	RW_WRITE 2	/* Write request */
			#define	RW_EXEC	 3	/* Execute procedure */
			#define	RW_RESET 4	/* Reset board */
			#define	RW_CONT  5	/* Break out of spinloop */

	/*
	 *	For read/write requests, what device to access
	 */
	host_uint32	rw_type;
			#define	RW_RAM	0
			#define	RW_CONC	1
			#define	RW_DSP	2

	/*
	 *	For CONC and DSP types, the DSP or concentrator number
	 *	For other types, the cpu number for request
	 *	For DSP types - this also indicates PM vs DM:
	 *		0x000tnnnn
	 *			t => memory type & overlay (RW_DM/RW_PM)
	 *			nnnn => dsp number.
	 */
	host_uint32	rw_subtype;
			#define	RW_DM	0		/* access DM */
			#define	RW_PM	(1 << 16)	/* access PM */
			#define RW_DSP_MEM(x)		((x) & RW_PM)
			#define	RW_DSP_NUM(x)		((x) & 0x0000ffff)

	/*
	 *	Now the address, size, and buffer
	 */
	host_uint32	rw_addr;	/* Memory/jump address */
	host_uint32	rw_size;	/* Read/write length */

	pad_32		pad[3];

	shared_uint8	rw_data[128];	/* Data buffer */

} RWDATA;

/*
 *	The common portion of the global data (cacheline-32 safe)
 */
typedef struct global_common
{
	/*
	 *	Magic number of currently running firmware
	 */
	board_uint32	magic;
			#define	MAGIC_BOOT	MKMAGIC('b','o','o','t')
			#define	MAGIC_POST	MKMAGIC('p','o','s','t')
			#define	MAGIC_FEP	MKMAGIC('g','l','b','l')

	/*
	 *	Initialization status of currently running firmware
	 *
	 *	Values of 0 thru (STATUS_RUN-1) mean the firmware is in the
	 *	midst of initialization.  If this value gets "stuck" in this
	 *	range, the board firmware has failed initialization
	 *	for some reason.  The actual reason for failure may
	 *	be indicated by this value, or the firmware is free
	 *	to provide additional information concerning the
	 *	reason in additional structure members below.
	 *
	 *	A value >= STATUS_RUN means the firmware is in its normal
	 *	running state.  Its background main loop or scheduler is fully
	 *	operating.
	 *
	 *	STATUS_RUN does not necessarily mean that the firmware
	 *	encountered no errors.  For example, the BOOT firmware
	 *	could have detected that there is no valid POST in flash.
	 *	It indicates this is in an additional member below, but
	 *	proceeds into STATUS_RUN.  This guarantees to the driver
	 *	that the BOOT is executing out of RAM and is waiting for
	 *	the driver to write a valid POST image to flash and then
	 *	prod it with a reset.  Likewise, the POST may determine
	 *	that non-critical hardware has failed on the board.  It
	 *	will indicate the exact failure(s) in additional members
	 *	below, then proceed into STATUS_RUN state.  This indicates
	 *	to the driver that, should anybody desire, they can do
	 *	a "cu" to the POSTs TCL interpreter and perform more
	 *	in-depth failure analysis.
	 *	
	 */
	board_uint32	status;
			#define	STATUS_INIT	0
			#define	STATUS_RUN	256

	/*
	 *	This is an arbitrary revision number assigned to the
	 *	firmware for identification and compatibility purposes.
	 *	The process assigning revision numbers is TBD.  Could
	 *	be time is seconds since the epoch, could be a build number,
	 *	could be a number incremented once per release.
	 */
	board_uint32	revision;

	/*
	 *	All firmware must provide a heartbeat that increments
	 *	this counter once around the lowest priority background
	 *	main loop, but no less than twice per second.  The host
	 *	uses this to determine if the board has gone insane.
	 */
	board_uint32	heartbeat;

	/*
	 *	The endianess of the board CPU is indicated here.
	 *	Non-zero means bigendian.  This is provided for
	 *	informational purposes only.  The host driver is not
	 *	expected to have to use this information (except,
	 *	possibly, for debugging tools which peer into private
	 *	board RAM).
	 */
	board_uint32	bigendian_board;	

	/*
	 *	we need padding here, to force rw structure onto a
	 *	cacheline boundary.
	 */
	pad_32		pad1[5];

	/*
	 *	The read-write structure.  This structure allows the
	 *	host to command arbitrary reads and writes of memory,
	 *	force execution to call a specific address, and to
	 *	force a software reset on hardware that does not have a
	 *	host-accessable register to cause a hardware reset,
	 *	such as the Galileo-9.
	 *
	 *	There are three important uses for this structure that
	 *	should be pointed out.
	 *	1) RW_RESET is used by the host driver after writing a
	 *	   new POST in flash.
	 *	2) RW_RESET is used by the host driver when it unloads
	 *	   so that the BOOT and POST are re-executed immediately
	 *	   so that the board will be ready for the next time the
	 *	   driver is loaded.
	 *	3) RW_EXEC is used by the host driver to transfer control
	 *	   to the FEP after the driver has loaded the FEP into
	 *	   memory on the board.
	 *	
	 */
	RWDATA		rw;

} GLOBAL_COMMON;

/*
 *	When the BOOT program is running, this is its global data.
 *	By decree, all data in this structure is little endian.
 *	This structure is cacheline-32 safe, even though the
 *	boot program always uses uncached accesses for reliability.
 */
typedef struct global_boot_data
{
	/*
	 *	The common data required by all firmware
	 */
	GLOBAL_COMMON	common;

	/*
	 *	Failure of the CRC of the flash containing the POST firwmare,
 	 *	or anything else that the BOOT cares about is indicated here
	 *	in this bitmask.  The driver can use this information to
	 *	determine if it should try to reporgram the post in flash,
	 *	or just give up.  This data is valid only if BOOT is in
	 *	the STATUS_RUN state.  If no failures are detected, the
	 *	BOOT never enters the STATUS_RUN state -- it simply loads
	 *	the POST and jumps to it.
	 */
	board_uint32	failure;
			#define	FAIL_OTHER	0x80000000
			#define	FAIL_POSTFLASH	0x40000000
			#define		FAIL_POSTJUMP	1
			#define		FAIL_POSTCRC	2
			#define		FAIL_POSTLENGTH	3
			#define		FAIL_POSTHEADER	4
			#define	FAIL_RAMTEST	0x20000000

	/*
	 *	If RAM has failed, here is the address and data pattern
	 */
	board_uint32	ramaddr;
	board_uint32	ramdata;

	pad_32		pad1[7];

} GLOBAL_BOOT_DATA;

/*
 *	This is the format for error reports from the POST. If
 *	errors exist, the error_list pointer will point to a
 *	linear array of these structures. They will be at least
 *	error_count informative entries in this array, as well
 *	as an arbitrary number of no-op entries. The list is always
 *	terminated by an end-of-list entry. Neither nop or eol
 *	entries contribute to error_count.
 */
typedef struct post_error_report
{
	/*
	 * Indentify the failing component referred to by this entry.
	 */
	board_uint16	identifier ;
			#define	POST_ERROR_NOP		0x0000

			#define	POST_ERROR_CPU		0x0100
			#define	POST_ERROR_MEM		0x0101
			#define	POST_ERROR_GPP		0x0102
			#define	POST_ERROR_PCI		0x0103
			#define	POST_ERROR_DMA		0x0104
			#define	POST_ERROR_STAC		0x0105
			#define	POST_ERROR_MVIP		0x0106

			#define	POST_ERROR_DS1_LIU	0x0200
			#define	POST_ERROR_ST_LIU	0x0201
			#define	POST_ERROR_U_LIU	0x0202
			#define	POST_ERROR_FRAMER	0x0203
			#define	POST_ERROR_PRI_D	0x0204
			#define	POST_ERROR_BRI_D	0x0205
			#define	POST_ERROR_CODEC	0x0206

			#define	POST_ERROR_DSP		0x0300

			#define	POST_ERROR_EOL		0xffff

			/*
			 * The potential impact of the error is
			 * indicated as board/port/channel.
			 */
			#define	POST_ERROR_LEVEL(x)	(0x0f00 & (x))
			#define	POST_BOARD_ERROR	0x0100
			#define	POST_PORT_ERROR		0x0200
			#define	POST_CHANNEL_ERROR	0x0300
	/*
	 * For port and channel level errors, this identifies
	 * the specific instance.
	 */
	board_uint16	ordinal ;

	/*
	 * The syndromes are identifier specific and TBD.
	 */
	board_uint32	syndrome[3] ;
} POST_ERROR_REPORT ;

/*
 *	When the POST program is running, this is its global data.
 *	By decree, all data in this structure is little endian.
 *	This structure is cacheline-32 safe.
 */
typedef struct global_post_data
{
	/*
	 *	The common data required by all firmware
	 */
	GLOBAL_COMMON	common;

	/*
	 *	Hardware information detected by POST and available
	 *	for use by the driver and the FEP.
	 */
	board_uint32	board_type ;
			#define	POST_TYPE_HOUSTON_T1	0x0001
			#define	POST_TYPE_HOUSTON_E1	0x0002
			#define	POST_TYPE_LONDON_U	0x0003
			#define	POST_TYPE_LONDON_ST	0x0004
			#define	POST_TYPE_CHASKA	0x0005

	board_uint8	serial[32] ;
	
	board_uint32	memsize;	/* Bytes of RAM detected by POST */
	board_uint32	nport;	 	/* Physical # of ports on board */
	board_uint32	cpp ;		/* # of channels per port */
	board_uint32	nchan ;		/* # of channels physically present */

	board_uint32	error_count ;	/* count of errors found. */
	volatile POST_ERROR_REPORT *error_list ;/* pointer to list of errors */

	pad_32		pad1[1];	/* Next member is host-written */


	/*
	 *	Host endianess.  The host can indicate its endianess
	 *	here.  This is typically written by the host driver
	 *	just before it loads and executes the FEP.  The FEP
	 *	saves this information before switching the global
	 *	area to its own area.
	 *
	 *	AT SOME FUTURE TIME, the FEP *may* be modified so that
	 *	its global data and channel, event, and command structures
	 *	are automatically set to the endianess of the host.  But
	 *	this is not currently implemented.
	 */
	host_uint32	bigendian_host;	

	pad_32		pad2[7];

} GLOBAL_POST_DATA;

	
/*
 *	When the FEP program is running, this is its global data.
 *	By decree, all data in this structure is little endian.
 *	This structure is cacheline-32 safe.
 */
typedef struct global_fep_data
{
	/*
	 *	The common data required by all firmware
	 */
	GLOBAL_COMMON	common;

	/*
	 *	Other FEP data
	 */
	board_uint32	chan;		/* Offset of channel structures */
	board_uint32	npayload_chans;	/* Count of data chanels. */
	board_uint32	ncontrol_chans;	/* Count of additional channels */
	board_uint32	command_q;      /* Offset of command queue */
	board_uint32	event_q;        /* Offset of event queue */
	board_uint32	panic;       	/* Offset of panic structure */
	board_uint32	newchan_version; /* Offset of header revision string */

	/* no padding needed so far */

} GLOBAL_FEP_DATA;


#endif
