/*****************************************************************************
 * Copyright (c) 1988-97 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1997
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/*
 * $Id: phd.h,v 1.5 1997/10/21 20:48:42 gary Exp $
 */

#include "types.h"

#define	NUM_QUICC_TX_ELEMENTS	16	/* Must be a power of 2 */
#define	NUM_QUICC_RX_ELEMENTS	16	/* Must be a power of 2 */

#define	NUM_LOCAL_RING_ELEMENTS	16	/* Must be a power of 2 */
#define	NUM_COMMAND_ELEMENTS	128	/* Must be a power of 2 */
#define	NUM_CHANNELS			32

#define	NUM_TXBDS	NUM_QUICC_TX_ELEMENTS
#define NUM_RXBDS	NUM_QUICC_RX_ELEMENTS

#define	RAM_BASE		0x00000000L
//#define	SHARED_INIT_OFFSET	0x00000000L

//#define	SMC_DESC_OFFSET 0 
//#define SMC_RXBUF_SIZE	20
//#define	SMC_TXBUF_SIZE	100

//#define	SMC_RX_DESCS	4
//#define	SMC_TX_DESCS	4


/*
 * Tx and Rx state variable values (hd_txstate and hd_rxstate)
 * PAUSED, TXING and READY only apply to the half-duplex mode
 */
#define OFF         0		/* SCC Disabled				*/
#define IDLE        1		/* No Tx activity allowed or required	*/
#define PAUSED      2		/* RTS asserted; waiting for CTS	*/
#define	TXING       3		/* Transmitting frames			*/
#define	READY       4		/* Tx line idle, but RTS & CTS asserted	*/
#define	DROPPING    5		/* RTS dropped; waiting for CTS drop	*/

#define CRCSIZE	    2		/* Number of CRC bytes included in rx buff */


/*
 * In the following structure definitions, (M) indicates that the main
 * processor sets the contents of the field, and (P) indicates that the
 * PowerQUICC processor sets the contents of the field.
 */

/* Outbound (Main to PowerQUICC) data buffer descriptor */
typedef struct quicc_tx_element
{
	volatile uint8  *location ;	/* (M) Starting address of buffer */
	volatile void   *mblk ;		/* (M) Address of controlling mblk */
	volatile uint32 length ;	/* (M) Size of buffer, expressed in bytes */
	volatile uint32 flags ;		/* (M/P) Error/Control flags */
} quicc_tx_element_t ;

/* Inbound (PowerQUICC to Main) data buffer descriptor */
typedef struct quicc_rx_element
{
	volatile uint8  *location ;	/* (M) Starting address of buffer */
	volatile void   *mblk ;		/* (M) Address of controlling mblk */
	volatile uint32 datasize ;	/* (P) Actual data buffer size */
	volatile uint32 flags ;		/* (P) Error/Control flags */
} quicc_rx_element_t ;

typedef struct quicc_tx_channel
{
	volatile uint32 head ;		/* (M) Index of next unused slot */
	volatile uint32 tail ;		/* (P) Index of next element to process */
	volatile uint32 shadow_tail ;	/* (M) Index of next element to clean up */
	volatile quicc_tx_element_t buffer[NUM_QUICC_TX_ELEMENTS] ;
} quicc_tx_channel_t ;

typedef struct quicc_rx_channel
{
	volatile uint32 head ;		/* (P) Index of next unused buffer element */
	volatile uint32 tail ;		/* (M) Index of next element to process */
	volatile uint32 shadow_tail ;	/* (M) Index of next buffer to refresh */
	volatile quicc_rx_element_t buffer[NUM_QUICC_RX_ELEMENTS] ;
} quicc_rx_channel_t ;

typedef struct quicc_cmd_queue
{
	volatile uint32 head ;		/* (M) Index of next unused command slot */
	volatile uint32 tail ;		/* (P) Index of next command to process */
	volatile uint32 command[NUM_COMMAND_ELEMENTS] ;
} quicc_cmd_queue_t ;

typedef struct scc_parm_structure
{
	volatile uint8  return_code[4] ;/* (P) Results of operation are placed here */
	volatile uint32 maxframe ;		/* (M) Maximum frame size */
	volatile uint32 buffer ;		/* (M) Size of each receive buffer */
	volatile uint32 baud ;			/* (M) Baud rate (0 for external clocking) */
	volatile uint32 options ;		/* Communications Options */
	volatile uint8  fill_mask[32] ;	/* TDM bit mask */
	volatile uint32 mode ;			/* HDLC or transparent */
	volatile uint32 timeslot_mask ;	/* timeslots desired */
	volatile uint32 fnum ;
	volatile uint32 crc ;			/* CRC-32 or CRC-16 */
	volatile uint32 inv ;			/* invert data? */
	volatile uint32 bsize ;
	volatile uint32 dtmf ;			/* Turn DTMF on/off */
} scc_parm_t ;


/*
 * Channel stats from the PowerQuicc
 */
typedef	struct iwan_chan_stats
{
	int sf_err ;
	int loss_err ;
	int crc_err ;
	int nob_err ;
	int lfd_err ;
	int ra_err ;
	int rof_err ;
	int no_inn_space ;
	int no_wan_mp ;
	int no_fe_and_no_c ;
	int tx_size_err;
	int rx_size_err;
	int tx_prep;
	int tx_good;
	int rx_good;
	int t_hi ;
	int t_fi ;
	int t_ifc ;
	int t_sf ;
	int t_err ;
	int t_fo ;
	int r_hi ;
	int r_fi ;
	int r_ifc ;
	int r_sf ;
	int r_err ;
	int r_fo ;
} iwan_chan_stats_t ;

/*
 * Connect configuration information for IWAN
 */
typedef	struct connect_cfg
{
	uint32		baud ;
	uint32		options ;
	uint8		fill_mask[32] ;
	uint32		mode ;
	uint32		timeslot_mask ;
	uint32		fnum ;
	uint32		crc ;
	uint32		inv ;
	uint32		bsize ;
	uint32		dtmf ;
} connect_cfg_t ;

// connect_cfg.mode defines
#define		HDLC_MODE			1
#define		TRANSPARENT_MODE	2

// other related defines
#define		CRC32				1
#define		CRC16				2

/*
 * This structure is used by the main processor entity to track the state
 * of a channel.
 */
typedef struct scc_chan
{
	volatile uint8              state ;
	volatile uint16				scc ;
	volatile uint32             channel ;
	volatile void               *wanp ;
	volatile uint32             refresh_mask ;
	volatile uint32             tx_command_word ;
	volatile uint32             local_rx_ring_head ;
	volatile uint32             local_rx_ring_tail ;
	volatile uint32             TxOFlowTime ;
	volatile void               *local_rx_ring[NUM_LOCAL_RING_ELEMENTS] ;
	volatile quicc_tx_channel_t	*tx_chan ;
	volatile quicc_rx_channel_t	*rx_chan ;

	volatile uint32				max_frame_len ;
	volatile uint32				default_buf_len ;
	volatile uint32				timeslot_mask ;

	volatile connect_cfg_t		connect_cfg ;
	volatile iwan_chan_stats_t	stats ;

	volatile uint32				trace_seq_num ;
	volatile void			   *trace_msg ;
} scc_chan_t ;


/*
 * SCC_CHAN->state values
 */
#define	TX_ACTIVE		0x0001
#define	RX_ACTIVE		0x0002
#define	RX_REFRESH_REQ	0x0004
#define	RX_INITIALIZING	0x0008
#define	TX_BLOCKED		0x0010


/*
 * This structure is located at an agreed-upon location in shared
 * memory.
 */

#define	INIT_STRUCTURE_OFFSET		PPCSHAREDRAMSTRUCTURE

/* Global arrays */
typedef struct shared_ram_init
{
	volatile quicc_tx_channel_t tx_array[2][NUM_CHANNELS] ;

	volatile quicc_rx_channel_t rx_array[2][NUM_CHANNELS] ;

	volatile quicc_cmd_queue_t command_queue ;

	volatile scc_parm_t shared_structure[2][NUM_CHANNELS] ;

	volatile unsigned long shared_timer ;

	volatile long   maincodebodystart ;
	volatile long   maincodebodyend ;
	volatile long   mainrodatabodyend ;
	volatile long   maindatabodystart ;
	volatile long   maindatabodyend ;
	volatile long   configvalid ;
	volatile long   memconfigindex ; 
	volatile long   mainbodyplxlocation ;
	volatile long   *mainbodyintr860location ;

	int 	(*ev_loop)() ;

	volatile int	CmdSemaCnt ;

} shared_ram_init_t ;


/* Flags for "state" field */
#define	CH_USED			0x01
#define	CH_INITIALIZING	0x02
#define	CH_ACTIVE		0x04
#define	CH_REFRESH_REQ	0x08
#define	CH_TX_BLOCKED	0x10

/* Possible command values */
#define	CMD_TX				0x10000000L
#define	CMD_START			0x20000000L
#define	CMD_STOP			0x40000000L

#define	CMD_MASK			(CMD_TX|CMD_START|CMD_STOP)
#define	CMD_CHANNEL_MASK	0x0000001FL
#define CMD_SCC_MASK		0x00000080L

/* Tx descriptor flags */
#define	TX_END_OF_FRAME	0x0800L
#define	TX_CONTINUOUS	0x0200L

/* Rx descriptor flags */
#define	RX_END_OF_FRAME	0x0800L
#define	LARGE_FRAME		0x0020L
#define	NON_OCTET_FRAME	0x0010L
#define	ABORT			0x0008L
#define	CRC				0x0004L
#define	RX_ERR_FLAGS	(LARGE_FRAME|NON_OCTET_FRAME|ABORT|CRC)

