
/*
 Copyright 1999 by Digi International (www.digi.com)

 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 
 implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
 PURPOSE.  See the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
 *	$Id: gal9mmap.h,v 1.7 1999/09/03 15:27:18 dickl Exp $
 *
 *	This file is used by both the linker directives and sometimes by
 *	mere source code.  Absolutely the only thing that can be in here
 *	are #defines of constants and #ifdefs.  NO C CODE!!!!!
 */

/*
 * Size of onboard RAM.  Only the BOOT and the POST should be using
 * this size, since they must test RAM.  The FEP and device drivers
 * would be smart to use the variable in the global data provided for
 * this purpose, so they won't need recompiling if boards are ever
 * built with more RAM.
 */
#define	RAM_SIZE	(4096*1024)

/*
 * Offsets in RAM interesting to both host and 4640 processor.
 */
#define	GLOBAL_DEBUG_OFFSET	0x0200
#define	GLOBAL_DATA_OFFSET	0x1000

#define	BOOT_CODE_SIZE		(32 * 1024)
#define	BOOT_CODE_OFFSET	(RAM_SIZE - BOOT_CODE_SIZE)

#define	POST_CODE_SIZE		(512 * 1024)
#define	POST_CODE_OFFSET	(RAM_SIZE - POST_CODE_SIZE)

/*
 * Offsets from CS0 interesting to the 4640 processor.
 * These 8-bit devices are not accessable from the host.
 */
#define	UARTB_OFFSET	0x00000
#define	UARTA_OFFSET	0x00008


/*
 * Offsets from CS1/CS3 interesting to both host and the 4640.
 * BOOTCS is accessed using the 4th PCI base address from the host side.
 * CS1 is located at CS1_ADDR from the 4640 side.  Both chip selects
 * address the same 8 bit devices.
 */
#define	EPROM_OFFSET	0x00000

/*
 * Offsets from CS2/BOOTCS interesting to the 4640 processor.
 * BOOTCS is accessed using the 4th PCI base address from the host side.
 * CS2 is located at CS2_ADDR from the 4640 side.  Both chip selects
 * address the same 32 bit devices.
 */
#define	FLASH_OFFSET	0x00000

/* 
 * Things interesting only to the 4640 processor.
 */
#define DP_RAM_ADDR	0xa0000000
#define REG64011_ADDR	0xb4000000

#define	CS0_ADDR	0xBC000000
#define	CS1_ADDR	0xBC800000
#define	CS2_ADDR	0xBFC00000

#define	FLASH_ADDR	(CS2_ADDR + FLASH_OFFSET)

/*
 *	Deprecated
 */
#define COMM_OFFSET	0x1000
