
/*****************************************************************************
 * Copyright (c) 1988-95 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1995
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/*
 * @(#) $Id: pac.h,v 1.5 1998/01/12 17:51:47 meern Exp $
 */
#define NUM_PAC_CTRLS NUM_T1E1_DEVS

#define PAC_CTRL_ADDR_0 0xA2020000 
#define PAC_CTRL_ADDR_1 0xA2030000

#define PAC_SR0_FACI	0x01
#define	PAC_SR0_RACI	0x02
#define	PAC_SR0_FAEI	0x04
#define	PAC_SR0_PDIAGI	0x08
#define PAC_SR0_XSFEI	0x10
#define	PAC_SR0_RSFEI	0x20
#define	PAC_SR0_ECRCEI	0x40
#define PAC_SR0_BIT7	0x80 

#define	PAC_SR1_OOF	0x01
#define	PAC_SR1_LSA	0x02
#define	PAC_SR1_AIS	0x04
#define	PAC_SR1_OOFLR	0x08
#define	PAC_SR1_LTS0MA	0x10
#define	PAC_SR1_LTS16MA	0x20
#define	PAC_SR1_FSTATE	0x40
#define	PAC_SR1_BIT7	0x80

#define	PAC_SR2_RFA0	0x01
#define PAC_SR2_BIT1	0x02
#define	PAC_SR2_BIT2	0x04
#define	PAC_SR2_RMA16	0x08
#define	PAC_SR2_RJYA	0x10
#define	PAC_SR2_BIT5	0x20
#define	PAC_SR2_BIT6	0x40
#define	PAC_SR2_BIT7	0x80

#define	PAC_SR3_LFV	0x01
#define	PAC_SR3_FBE	0x02
#define	PAC_SR3_CFA	0x04
#define	PAC_SR3_BOF	0x08
#define	PAC_SR3_BUF	0x10
#define	PAC_SR3_FSFT	0x20
#define	PAC_SR3_LLBON	0x40
#define	PAC_SR3_LLBOFF	0x80

#define	PAC_SR4_ES	0x01
#define	PAC_SR4_BES	0x02
#define	PAC_SR4_SES	0x04
#define	PAC_SR4_CRCRST	0x08
#define	PAC_SR4_REBEA0	0x10
#define	PAC_SR4_REBEA1	0x20
#define	PAC_SR4_OFSTATE	0x40
#define	PAC_SR4_CSFA	0x80

#define PAC_SR22_RB1W   0x10
#define PAC_SR22_RB1NW  0x20


#define	PAC_PR0_FACIE	0x01
#define	PAC_PR0_RACIE	0x02
#define	PAC_PR0_FAEIE	0x04
#define	PAC_PR0_PDIE	0x08
#define	PAC_PR0_XSFEIE	0x10
#define	PAC_PR0_RSFEIE	0x20
#define	PAC_PR0_ECRCIE	0x40
#define	PAC_PR0_MSTRIE	0x80

#define	PAC_PR1_FCOPT0	0x01
#define	PAC_PR1_FCOPT1	0x02
#define	PAC_PR1_FCOPT2	0x04
#define	PAC_PR1_FCOPT3	0x08
#define	PAC_PR1_FCOPT4	0x10
#define	PAC_PR1_LCOPT0	0x20
#define	PAC_PR1_LCOPT1	0x40
#define	PAC_PR1_LCOPT2	0x80

#define	PAC_PR1_DS1_ATT_ESF	0
#define PAC_PR1_DS1_ATT_D4	PAC_PR1_FCOPT0	
#define PAC_PR1_DS1_DDS		PAC_PR1_FCOPT1
#define PAC_PR1_DS1_DDS_FDL	PAC_PR1_FCOPT1+PAC_PR1_FCOPT0
#define	PAC_PR1_DS1_SLC96	PAC_PR1_FCOPT2
#define	PAC_PR1_DS1_ANSI_D4	PAC_PR1_FCOPT2+PAC_PR1_FCOPT0
#define	PAC_PR1_DS1_ANSI_ESF	PAC_PR1_FCOPT2+PAC_PR1_FCOPT1+PAC_PR1_FCOPT0

#define PAC_PR1_CEPT_CCS	PAC_PR1_FCOPT3
#define	PAC_PR1_CEPT_PCS0	PAC_PR1_FCOPT3+PAC_PR1_FCOPT0
#define	PAC_PR1_CEPT_PCS1	PAC_PR1_FCOPT3+PAC_PR1_FCOPT1

#define PAC_PR1_CEPT_CRC4_CCS	PAC_PR1_FCOPT3+PAC_PR1_FCOPT2
#define	PAC_PR1_CEPT_CRC4_PCS0	PAC_PR1_FCOPT3+PAC_PR1_FCOPT2+PAC_PR1_FCOPT0
#define PAC_PR1_CEPT_CRC4_PCS1	PAC_PR1_FCOPT3+PAC_PR1_FCOPT2+PAC_PR1_FCOPT1

#define	PAC_PR1_B8ZS		0
#define	PAC_PR1_ZCS		PAC_PR1_LCOPT0
#define	PAC_PR1_HDB3		PAC_PR1_LCOPT1
#define	PAC_PR1_AMI		PAC_PR1_LCOPT0 + PAC_PR1_LCOPT1

#define PAC_PR2_AXRFA	0x01
#define	PAC_PR2_AXRMA	0x02
#define	PAC_PR2_ARCHSQ	0x04
#define	PAC_PR2_ARSGSQ	0x08
#define	PAC_PR2_ALLB	0x10

#define PAC_PR3_DXRFA	0x01
#define PAC_PR3_DXJRFA  0x02
#define PAC_PR3_DXRMA   0x04
#define PAC_PR3_DXDLSQ  0x08
#define PAC_PR3_DXCHSQ	0x10
#define	PAC_PR3_FAIS    0x20
#define PAC_PR3_LDTS    0x40
#define PAC_PR3_TFTS1D	0x60
#define	PAC_PR3_HDTS	0x80
#define	PAC_PR3_UNFAIS	0xA0
#define	PAC_PR3_TTS_CLEAR 0xE0 ;

#define PAC_PR4_DRCHSQ  0x01
#define PAC_PR4_DRSGSQ  0x02
#define PAC_PR4_DRRFRM	0x04
#define	PAC_PR4_DRSI	0x08
#define PAC_PR4_LOOP_CLEAR ~0x30
#define PAC_PR4_LLB	0x10 
#define PAC_PR4_PLBPF	0x20
#define PAC_PR4_PLBRF	0x30
#define PAC_PR4_XLLBON	0x40
#define PAC_PR4_XLLBOFF	0x80

#define PAC_PR7_XEB     0x80

#define	PAC_PR9_SWP0	0x00
#define	PAC_PR9_SWP1	0x01
#define	PAC_PR9_SWP2	0x02
#define	PAC_PR9_SWP3	0x03
#define	PAC_PR9_SWP24	0x04
#define	PAC_PR9_PLLR	0x08
#define	PAC_PR9_CHIMM	0x10
#define	PAC_PR9_SFSEL	0x20

#define	PAC_PR10_TSIG	0x01
#define	PAC_PR10_STOMP	0x02
#define	PAC_PR10_ASM	0x04
#define	PAC_PR10_CSS9ST	0x08
#define	PAC_PR10_MOSCCS	0x10
#define	PAC_PR10_IRSM	0x20
#define	PAC_PR10_FRMD	0x40

#define	PAC_PR11_XICRC 	0x80
#define PAC_PR11_BLB	0x40
#define	PAC_PR11_OCE	0x20
#define PAC_PR11_RSTRT	0x10
#define	PAC_PR11_RST	0x08
#define	PAC_PR11_CKSEL	0x04
#define	PAC_PR11_CMS	0x02
#define	PAC_PR11_HFLF	0x01

#define	PAC_PR13_XOFF(x)	((x) & 0x07)
#define	PAC_PR13_HWYEN		0x08
#define	PAC_PR13_ROFF(x)	(((x) & 0x07) << 4)
#define	PAC_PR13_FE		0x80

#define	PAC_PR14_XBYOFF(x)	((x) & 0x3f)
#define	PAC_PR14_XCE		0x40
#define	PAC_PR14_XLBIT		0x80

#define	PAC_PR15_RBYOFF(x)	((x) & 0x3f)
#define	PAC_PR15_RCE		0x40
#define	PAC_PR15_RLBIT		0x80

/* 
 *These mask bits are used to clear the COR bits in the status bits
 * before they are stored for previous states. IT is VERY important
 * that these bits be used to prevent two transitions in a row. One
 * for set and another for not set.
 *
 * Even more disasterous would be to constantly clear a bit that is set
 * as long as a condition exists. This would result in a constant transition
 * from 0 to 1, being reported EVERY time the poller came around.
 */

#define	PAC_STAT1_MASK (((PAC_SR1_LSA | PAC_SR1_AIS | PAC_SR1_OOFLR | \
			 PAC_SR1_LTS0MA | PAC_SR1_LTS16MA | \
			 PAC_SR1_FSTATE) << 8) | \
			((PAC_SR2_RFA0 | PAC_SR2_RMA16 | PAC_SR2_RJYA ) << 16))

#define	PAC_STAT2_MASK 0

#define PAC_STAT1_FACI	0x00000001
#define	PAC_STAT1_RACI	0x00000002
#define	PAC_STAT1_FAEI	0x00000004
#define	PAC_STAT1_PDIAGI 0x00000008
#define PAC_STAT1_XSFEI	0x00000010
#define	PAC_STAT1_RSFEI	0x00000020
#define	PAC_STAT1_ECRCEI 0x00000040

#define	PAC_STAT1_OOF	0x00000100
#define	PAC_STAT1_LSA	0x00000200
#define	PAC_STAT1_AIS	0x00000400
#define	PAC_STAT1_OOFLR	0x00000800
#define	PAC_STAT1_LTS0MA	0x00001000
#define	PAC_STAT1_LTS16MA	0x00002000
#define	PAC_STAT1_FSTATE	0x00004000

#define	PAC_STAT1_RFA0	0x00010000
#define	PAC_STAT1_RMA16	0x00080000
#define	PAC_STAT1_RJYA	0x00100000

#define	PAC_STAT1_LFV	0x01000000
#define	PAC_STAT1_FBE	0x02000000
#define	PAC_STAT1_CFA	0x04000000
#define	PAC_STAT1_BOF	0x08000000
#define	PAC_STAT1_BUF	0x10000000
#define	PAC_STAT1_FSFT	0x20000000
#define	PAC_STAT1_LLBON	0x40000000
#define	PAC_STAT1_LLBOFF 0x80000000


#define	PAC_STAT2_ES	0x00000001
#define	PAC_STAT2_BES	0x00000002
#define	PAC_STAT2_SES	0x00000004
#define	PAC_STAT2_CRCRST 0x00000008
#define	PAC_STAT2_REBEA0 0x00000010
#define	PAC_STAT2_REBEA1 0x00000020
#define	PAC_STAT2_OFSTATE 0x00000040
#define	PAC_STAT2_CSFA	0x00000080

/*
 * There are 23 Status regs, and 32 each of the Parameter & Signalling regs.
 */
#define	N_PAC_SR_REGS		23		/* 0x00 - 0x16 */
#define	N_PAC_UNDEF_REGS	9		/* 0x17 - 0x1f */
#define	N_PAC_RS_REGS		32		/* 0x20 - 0x3f */
#define	N_PAC_PR_REGS		32		/* 0x40 - 0x5f */
#define	N_PAC_TS_REGS		32		/* 0x60 - 0x7f */

typedef struct {
	uint32 sr[N_PAC_SR_REGS] ;		/* Status Registers */
	uint32 dummy[N_PAC_UNDEF_REGS] ;	/* Undefined Registers */
	uint32 rs[N_PAC_RS_REGS] ;		/* Rx Signalling Registers */
	uint32 pr[N_PAC_PR_REGS] ;		/* Parameter Registers */
	uint32 ts[N_PAC_TS_REGS] ;		/* Tx Signalling Registers */
} pac_ctrl_t ;

#define NUM_INTERVALS 96 
#define NUM_INTERVAL_ELEMENTS 	12

#define	INTERVAL_CRC_CNT 	0 
#define INTERVAL_ERR_CNT 	1
#define INTERVAL_ES_CNT		2	
#define	INTERVAL_BES_CNT	3
#define	INTERVAL_SES_CNT	4
#define	INTERVAL_FS_CNT		5
#define	INTERVAL_LFV_CNT	6
#define	INTERVAL_FBE_CNT	7
#define	INTERVAL_SLIP_CNT	8
#define INTERVAL_LOFC_CNT	9
#define INTERVAL_OOFSEC_CNT	10
#define	INTERVAL_UAS_CNT	11

#define	PAC_LOFC_CLEAR		0
#define	PAC_LOFC_DECLARE	1
#define	PAC_LOFC_UPTRANSITION   2
#define	PAC_LOFC_DOWNTRANSITION 3

/*
 * PAC Register names..
 */
#define	PAC_SR0			0
#define	PAC_SR1			1
#define	PAC_SR2			2
#define	PAC_SR3			3
#define	PAC_SR4			4
#define	PAC_SR5			5
#define	PAC_SR6			6
#define	PAC_SR7			7
#define	PAC_SR8			8
#define	PAC_SR9			9
#define	PAC_SR10		10
#define	PAC_SR11		11
#define	PAC_SR12		12
#define	PAC_SR13		13
#define	PAC_SR14		14
#define	PAC_SR15		15
#define	PAC_SR16		16
#define	PAC_SR17		17
#define	PAC_SR18		18
#define	PAC_SR19		19
#define	PAC_SR20		20
#define	PAC_SR21		21
#define	PAC_SR22		22

#define	PAC_RS0			32
#define	PAC_RS1			33
#define	PAC_RS2			34
#define	PAC_RS3			35
#define	PAC_RS4			36
#define	PAC_RS5			37
#define	PAC_RS6			38
#define	PAC_RS7			39
#define	PAC_RS8			40
#define	PAC_RS9			41
#define	PAC_RS10		42
#define	PAC_RS11		43
#define	PAC_RS12		44
#define	PAC_RS13		45
#define	PAC_RS14		46
#define	PAC_RS15		47
#define	PAC_RS16		48
#define	PAC_RS17		49
#define	PAC_RS18		50
#define	PAC_RS19		51
#define	PAC_RS20		52
#define	PAC_RS21		53
#define	PAC_RS22		54
#define	PAC_RS23		55
#define	PAC_RS24		56
#define	PAC_RS25		57
#define	PAC_RS26		58
#define	PAC_RS27		59
#define	PAC_RS28		60
#define	PAC_RS29		61
#define	PAC_RS30		62
#define	PAC_RS31		63

#define	PAC_PR0			64
#define	PAC_PR1			65
#define	PAC_PR2			66
#define	PAC_PR3			67
#define	PAC_PR4			68
#define	PAC_PR5			69
#define	PAC_PR6			70
#define	PAC_PR7			71
#define	PAC_PR8			72
#define	PAC_PR9			73
#define	PAC_PR10		74
#define	PAC_PR11		75
#define	PAC_PR12		76
#define	PAC_PR13		77
#define	PAC_PR14		78
#define	PAC_PR15		79
#define	PAC_PR16		80
#define	PAC_PR17		81
#define	PAC_PR18		82
#define	PAC_PR19		83
#define	PAC_PR20		84
#define	PAC_PR21		85
#define	PAC_PR22		86
#define	PAC_PR23		87
#define	PAC_PR24		88
#define	PAC_PR25		89
#define	PAC_PR26		90
#define	PAC_PR27		91
#define	PAC_PR28		92
#define	PAC_PR29		93
#define	PAC_PR30		94
#define	PAC_PR31		95

#define	PAC_TS0			96
#define	PAC_TS1			97
#define	PAC_TS2			98
#define	PAC_TS3			99
#define	PAC_TS4			100
#define	PAC_TS5			101
#define	PAC_TS6			102
#define	PAC_TS7			103
#define	PAC_TS8			104
#define	PAC_TS9			105
#define	PAC_TS10		106
#define	PAC_TS11		107
#define	PAC_TS12		108
#define	PAC_TS13		109
#define	PAC_TS14		110
#define	PAC_TS15		111
#define	PAC_TS16		112
#define	PAC_TS17		113
#define	PAC_TS18		114
#define	PAC_TS19		115
#define	PAC_TS20		116
#define	PAC_TS21		117
#define	PAC_TS22		118
#define	PAC_TS23		119
#define	PAC_TS24		120
#define	PAC_TS25		121
#define	PAC_TS26		122
#define	PAC_TS27		123
#define	PAC_TS28		124
#define	PAC_TS29		125
#define	PAC_TS30		126
#define	PAC_TS31		127

/*
 * Initial values for PAC configuration. These will vary according to
 * the target platform.
 */
extern	uint32	PacInitRegisters[] ;
