#ident "$Id: hd.h,v 1.9 1997/01/30 17:11:26 gary Exp $"
/*****************************************************************************
 * Copyright (c) 1988-95 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1995
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/******************************************************************
 *
 *  SpiderX25 - Wan Board Embedded Code
 *
 *  Copyright 1991 Spider Systems Limited
 *
 *  HD.H
 *
 ******************************************************************/

/*
 *      $RCSfile: hd.h,v $
 *      %Q% %P%
 *      $Id: hd.h,v 1.9 1997/01/30 17:11:26 gary Exp $
 *
 *      Last delta created       $Date: 1997/01/30 17:11:26 $
 *      This file extracted     %T% %H%
 *
 *	Modifications:
 *
 *	16 Mar 89	DJMM	Changed state values (for CTS handling).
 *	 8 May 90	MV	Added support for MVME333 board.
 *	25 Oct 90	MV	Integrated DJMM's DMA code for MVME333.
 *				1. Now use unchar, etc instead of uint*.
 *				2. Added DMAC registers and Tx structure.
 *				3. Rx ISR conditionally compiled.
 *	Jul 1991	GM	amended to be more generic
 *      03 Apr 92	CHY	Add dcd flutter timer in hdlc structure
 */

#define NSCCS       2		/* Number of SCCs supported		*/
#define NTXFRAGS    4		/* Maximum no. of Tx message fragments  */

#define	NTXRING     8		/* Entries in Tx ring			*/

#define NRXRING	    16
#define NHDRING	    32

/*
 * Tx and Rx state variable values (hd_txstate and hd_rxstate)
 * PAUSED, TXING and READY only apply to the half-duplex mode
 */
#define OFF         0		/* SCC Disabled				*/
#define IDLE        1		/* No Tx activity allowed or required	*/
#define PAUSED      2		/* RTS asserted; waiting for CTS	*/
#define	TXING       3		/* Transmitting frames			*/
#define	READY       4		/* Tx line idle, but RTS & CTS asserted	*/
#define	DROPPING    5		/* RTS dropped; waiting for CTS drop	*/

#define CRCSIZE	    2		/* Number of CRC bytes included in rx buff */

/*
    This structure holds the timer specific data to run the
    calling procedure interface.
*/

typedef struct tmr
{
    thead_t thead;
    timer_t tmtab[NTIMS];
}  tmr_t;

struct sca_stat{
        union cdstats {
            struct xfer_stats{
                uint16 txstatus;
                uint16 rxstatus;
            }xstats;
            uint32 statustype;
            uint32 hdlcstatus;
            uint32 dmastatus;
            uint32 busstatus;
            uint32 buffstatus;
        }cds;
};

/* Device control structure (BEWARE: used also by SCC.ASM) */
struct hdlc
{
    /* General fields */
    caddr_t          hd_wanid;      /* WAN level slot id		    */
    uint16            hd_wanchan;      /* WAN chan id		    */
    struct hstats   *hd_stats;      /* Pointer to frame stats structure     */
    uint16           hd_maxframe;   /* Maximum frame length		    */

    /* SCA-specific fields */
    volatile struct sca        *hd_sca;   /* SCA address   			    */

    /* Channel states */
    uint8            hd_txstate;    /* Tx state (OFF, IDLE, ACTIVE, TXAGAIN)*/
    uint8            hd_rxstate;    /* Rx state (OFF, IDLE, ACTIVE)         */
    uint8            hd_hdplxticks; /* # of sys ticks to hold RTS high      */
    uint8            hd_hdplxidle;  /* Non-zero when Tx goes idle           */
    uint32           hd_hdplxtid;   /* ID of timeout used to drop RTS       */

    /* Rx ring pointers */
    struct rxring   *hd_rxtoring;   /* Rx ring 'to' pointer		    */
    struct rxring   *hd_rxdoring;   /* Rx ring 'do' pointer		    */
    struct rxring   *hd_rxfmring;   /* Rx ring 'from' pointer		    */
    struct rxring   *hd_rxrxring;   /* Rx ring 'from' pointer		    */

	int				 hd_rxhead ;    /* Receive Queue Tail        */
	int				 hd_rxtail ;    /* Receive Queue Head		 */
	int				 hd_rxcda  ;	/* Current DMA buffer index */
 
    uint16           hd_currtx_eda; /* Current TX EDA pointer */
    uint16           hd_txchaser;   /* Current TX cleanup pointer */
    int              hd_rxchaser;   /* Current RX refresh pointer */

    /* Tx and Rx control flags */
    uint32           hd_txoftime;   /* Tx message ring timeout		    */
    uint8            hd_txrjct;	    /* Tx message from WAN rejected	    */
    uint8            hd_txoflow;    /* Tx message ring is stalled	    */
    uint8            hd_rxavbl;	    /* Rx message reported to WAN	    */

    /* Modem control information */
    uint16	     hd_x21io;	    /* Register address for 55421 X21 chip  */
    uint16	     hd_x21data;    /* Register address for X21 data        */
    uint16	     hd_delaytm;    /* Delay time for DCE inoperable        */
    uint16	     hd_addr_sz;    /* Call proc. address size.             */
    mblk_t	*    hd_txmp;	    /* Transmit message.                    */
    caddr_t          hd_int;	    /* WAN to HDLC initialisation interface */
    uint16	     hd_extio;	    /* External io address for non-SCC lines */
    tmr_t	*    hd_tmr ;       /* Timers definitions used.		    */
    bufp_t	     hd_addr;	    /* Call proc. remote address.	    */
    uint8	     hd_chanmsk;    /* Channel mask for getting line values */
    uint8            hd_state;	    /* Current state of link    	    */
    uint8	     hd_qing;	    /* If WAN queueing thro' hdlx_tx failure*/
    uint8	     hd_refuseind;  /* Refuse incoming connect indication   */
    uint8	     hd_disregard;  /* Disregard incoming call command      */
    uint8	     hd_107mask;    /* Circuit 107 mask.		    */
    uint8	     hd_125mask;    /* Circuit 125 mask.		    */
    uint8	     hd_ctsenb;	    /* Determines if CTS interrupt enabled  */
    uint8	     hd_ctsint;	    /* Determines if CTS interrupt raised   */
    uint8	     hd_R_int;	    /* Status change interrupt received	    */
    uint8	     hd_I_stat;	    /* Status of I pin.			    */
    uint8	     hd_x21_mask;   /* Mask for current command register    */
    uint8	     hd_rxbyte;	    /* Byte received from the network.	    */
    uint8	     hd_async;	    /* Set when in asynchronous mode	    */
    uint8	     hd_txsz;	    /* Used for txing in call setup phases  */
    uint8            hd_enabled;
    uint8            hd_connrcvd;   /* WC_CONNECT rcvd from above */
    uint8            hd_mdmshadow;  /* Shadow register of DTR/RTS bits      */
};

/*
 * Note:
 *    The meaning of field 'hd_rxcnt' in the above structure
 *    depends on its value, as follows:
 *
 *	0x7FFF >= n >= 0x0001   Room for further n bytes in Rx buffer
 *	n==0x0000		Rx buffer is exactly full
 *	n==0xFFFF (-1)		One byte buffer overflow (might be first CRC)
 *	n==0xFFFE (-2)		>1 byte buffer overflow
 *	n==0xFFFD (-3)		No current Rx buffer (IDLE)
 *	0xFFFC >= n >= 0x8000   (not used)
 */

/* Rx ring entry */
struct rxring
{
    struct rxring   *rr_next;       /* Link to next ring entry		    */
    mblk_t          *rr_mp;         /* Frame message			    */
#if 0
    struct dma_desc *rr_des;        /* sca dma decriptor                    */
    uint8           *ram_base;      /* start of buffer in local dram        */
    uint16           rr_length;     /* Frame buffer length		    */
    uint16           rr_count;      /* Actual frame count		    */
    bufp_t           rr_base;       /* Frame buffer start address           */
    uint8            rr_state;      /* State (FREE, READY, BUSY or DONE)    */
#endif
};

/* Tx ring entry */
struct txring
{
    struct txring   *tr_next;       /* Link to next ring entry		    */
    struct uint8    *ram_base;      /* start of buffer in local dram        */
    struct dma_desc *tr_des;        /* sca dma descriptor */
    struct txfrag   *tr_firstfr;    /* Pointer to first fragment            */
    uint8            tr_firstch;    /* First character			    */
    uint8            tr_state;      /* State (FREE, READY, BUSY or DONE)    */
    struct txfrag
    {
	uint16   fr_count;          /* Number of bytes in fragment          */
	bufp_t   fr_base;           /* Fragment buffer start address        */
    }		     tr_frags[NTXFRAGS];
				    /* Fragments			    */
    uint16           tr_zcount;     /* Stopper (mapped to fr_count)         */
};

typedef struct hdlc hdlc_t;

