/*****************************************************************************
 * Copyright (c) 1988-97 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1997
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/*
 * $Id: phd.h,v 1.5 1997/10/21 20:48:42 gary Exp $
 */

#include "types.h"

#define	NUM_QUICC_TX_ELEMENTS	16	/* Must be a power of 2 */
#define	NUM_QUICC_RX_ELEMENTS	16	/* Must be a power of 2 */
#define	NUM_LOCAL_RING_ELEMENTS	16	/* Must be a power of 2 */
#define	NUM_COMMAND_ELEMENTS	64	/* Must be a power of 2 */
#define	NUM_CHANNELS		4

#define	RAM_BASE		0x00000000L
#define	SHARED_INIT_OFFSET	0x00000000L

#define	SMC_DESC_OFFSET 0 
#define SMC_RXBUF_SIZE	20
#define	SMC_TXBUF_SIZE	100

#define	SMC_RX_DESCS	4
#define	SMC_TX_DESCS	4


/*
 * Tx and Rx state variable values (hd_txstate and hd_rxstate)
 * PAUSED, TXING and READY only apply to the half-duplex mode
 */
#define OFF         	0		/* SCC Disabled				*/
#define IDLE        	1		/* No Tx activity allowed or required	*/
#define WAITING_FOR_CTS 2		/* RTS asserted; waiting for CTS	*/
#define	CTS_ACTIVE     	3		/* RTS & CTS asserted	*/
#define	RTS_DROPPING   	4		/* RTS to be dropped by timeout ; waiting for timeout	*/
#define	RTS_DROPPED	    5		/* RTS dropped; waiting for CTS drop	*/
#define WAITING_FOR_DCD_INACTIVE 6	/* Waiting for DCD to go inactive */


#define CRCSIZE	    2		/* Number of CRC bytes included in rx buff */


/*
 * In the following structure definitions, (M) indicates that the main
 * processor sets the contents of the field, and (P) indicates that the
 * PowerQUICC processor sets the contents of the field.
 */

/* Outbound (Main to PowerQUICC) data buffer descriptor */
typedef struct quicc_tx_element {
	volatile uint8  *location ;	/* (M) Starting address of buffer */
	volatile void   *mblk ;		/* (M) Address of controlling mblk */
	volatile uint32 length ;		/* (M) Size of buffer, expressed in bytes */
	volatile uint32 flags ;		/* (M/P) Error/Control flags */
} quicc_tx_element_t ;

/* Inbound (PowerQUICC to Main) data buffer descriptor */
typedef struct quicc_rx_element {
	volatile uint8  *location ;	/* (M) Starting address of buffer */
	volatile void   *mblk ;		/* (M) Address of controlling mblk */
	volatile uint32 datasize ;	/* (P) Actual data buffer size */
	volatile uint32 flags ;		/* (P) Error/Control flags */
} quicc_rx_element_t ;

typedef struct quicc_tx_channel {
	volatile int head ;		/* (M) Index of next unused slot */
	volatile int tail ;		/* (P) Index of next element to process */
	volatile int shadow_tail ;	/* (M) Index of next element to clean up */
	volatile quicc_tx_element_t buffer[NUM_QUICC_TX_ELEMENTS] ;
} quicc_tx_channel_t ;

typedef struct quicc_rx_channel {
	volatile int head ;		/* (P) Index of next unused buffer element */
	volatile int tail ;		/* (M) Index of next element to process */
	volatile int shadow_tail ;	/* (M) Index of next buffer to refresh */
	volatile quicc_rx_element_t buffer[NUM_QUICC_RX_ELEMENTS] ;
} quicc_rx_channel_t ;

typedef struct quicc_cmd_queue {
	volatile uint32 head ;		/* (M) Index of next unused command slot */
	volatile uint32 tail ;		/* (P) Index of next command to process */
	volatile uint32 command[NUM_COMMAND_ELEMENTS] ;
} quicc_cmd_queue_t ;

typedef struct scc_parm_structure {
	volatile uint8  return_code[4] ;	/* (P) Results of operation are placed here */
	volatile uint32 maxframe ;	/* (M) Maximum frame size */
	volatile uint32 buffer ;		/* (M) Size of each receive buffer */
	volatile uint32 baud ;		/* (M) Baud rate (0 for external clocking) */
	volatile uint32 options ;	/* Communications Options */
	volatile uint32 hdplx ;		/* Half-Duplex/Full-Duplex */
} scc_parm_t ;


/*
 * This structure contains the requested configuration parameters
 * for a particular SCC.
 */

typedef struct Channel_Config {
	volatile uint32 maxframe ;
	volatile uint32 baud ;
	volatile uint32 interface ;
	volatile uint32 buffer_sz ;
	volatile uint32 options ;
	volatile uint32 hdplx ;
} channel_config_t ;

/*
 * This structure is used by the main processor entity to track the state
 * of a channel.
 */
typedef struct scc_channel_structure {
	volatile uint8              state ;
	volatile uint8              modem_signal_shadow ;
	volatile void               *wanp ;
	volatile uint32             channel ;
	volatile uint32             refresh_mask ;
	volatile uint32             tx_command_word ;
	volatile uint32             local_rx_ring_head ;
	volatile uint32             local_rx_ring_tail ;
	volatile uint32             TxOFlowTime ;
	volatile void               *local_rx_ring[NUM_LOCAL_RING_ELEMENTS] ;
	volatile quicc_tx_channel_t *tx_chan ;
	volatile quicc_rx_channel_t *rx_chan ;
	volatile channel_config_t   config ;
	volatile hdlcstats_t	    stats ;
	volatile uint32				hdplxticks ;
	volatile uint32				hd_mdmshadow ;
	volatile uint32				hd_txstate ;
	volatile uint32				hd_rxstate ;
	volatile uint32				hd_hdplxidle ;
	volatile uint32				hd_hdplxtickid ;
	volatile uint32				hd_hdplxticks ;
	volatile uint32				hd_stop_disconnect ;
	volatile uint32				trace_seq_num ;
	volatile void			   *trace_msg ;
	volatile uint32				trace_last_modem ;
} scc_chan_t ;

/*
 * This structure is located at an agreed-upon location in shared
 * memory.
 */

#define	INIT_STRUCTURE_OFFSET		PPCSHAREDRAMSTRUCTURE

/* Global arrays */

typedef struct shared_ram_init {

	volatile quicc_tx_channel_t tx_array[NUM_CHANNELS] ;

	volatile quicc_rx_channel_t rx_array[NUM_CHANNELS] ;

	/*
	 *  quicc_cmd_queue_t structure.
	 */
	volatile quicc_cmd_queue_t command_queue ;
#define GSMRL_TCI   0x10000000
	/*
	 *  scc_parm_t structures.
	 */

	volatile scc_parm_t shared_structure[NUM_CHANNELS] ;

	volatile scc_chan_t scc_table[NUM_CHANNELS] ;

	/*
	 *  system time
	 */
	volatile unsigned long shared_timer ;

	/*
	 * shared cable ID array
	 */
	volatile unsigned char cable_id[NUM_CHANNELS] ;

	/*
	 * shared modem status array
	 */
	volatile unsigned char modem_status[NUM_CHANNELS] ;

	/*
	 *	Shared Array of Line Speeds for each port
	 */

	volatile unsigned long LineSpeed[NUM_CHANNELS] ;

	volatile unsigned long PortStatus[NUM_CHANNELS] ;

	volatile unsigned long RxGlitch[NUM_CHANNELS] ;

	volatile unsigned long TxGlitch[NUM_CHANNELS] ;

	volatile unsigned long RxPacketDisfc[NUM_CHANNELS] ;

	int 	(*ev_loop)() ;

	volatile int	CmdSemaCnt ;

	volatile long   maincodebodystart ;
	volatile long   maincodebodyend ;
	volatile long   mainrodatabodyend ;
	volatile long   maindatabodystart ;
	volatile long   maindatabodyend ;
	volatile long   configvalid ;
	volatile long   memconfigindex ; 
	volatile long   mainbodyplxlocation ;
	volatile long	*mainbodyintr860location ;	
	volatile char   SerialNum[12] ;
} shared_ram_init_t ;


/* Flags for "state" field */
#define	CH_USED		0x01
#define	CH_INITIALIZING	0x02
#define	CH_ACTIVE	0x04
#define	CH_REFRESH_REQ	0x08
#define	CH_TX_BLOCKED	0x10

/* Possible command values */
#define	CMD_TX		0x10000000L
#define	CMD_START	0x20000000L
#define	CMD_STOP	0x40000000L
#define	CMD_SETMODEM	0x80000000L
#define	CMD_MASK	(CMD_TX|CMD_START|CMD_STOP|CMD_SETMODEM)
#define	CHANNEL_MASK	0x000000FFL

/* Modem signal values for CMD_SETMODEM command*/
#define	SET_DTR		0x00000100L
#define	SET_RTS		0x00000200L
#define	SIGNAL_MASK	(SET_DTR|SET_RTS)

/* Tx descriptor flags */
#define	TX_END_OF_FRAME	0x00000800L
#define	UNDERRUN	0x00000002L
#define	CTS_LOST	0x00000001L
#define	TX_ERR_FLAGS	(UNDERRUN|CTS_LOST)

/* Rx descriptor flags */
#define	RX_END_OF_FRAME	0x00000800L
#define	DPLL_ERROR	0x00000080L
#define	LARGE_FRAME	0x00000020L
#define	NON_OCTET_FRAME	0x00000010L
#define	ABORT		0x00000008L
#define	CRC		0x00000004L
#define	OVERRUN		0x00000002L
#define	CD_LOST		0x00000001L
#define	RX_ERR_FLAGS	\
	(DPLL_ERROR|LARGE_FRAME|NON_OCTET_FRAME|ABORT|CRC|OVERRUN|CD_LOST)

