/*****************************************************************************
 * Copyright (c) 1988-95 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1995
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/********************************************************************
 ***  Primary Rate & SyncPort device assignments.
 ***
 ***  @(#) $Id: device.h,v 1.9 1997/03/03 16:54:55 gary Exp $
 ********************************************************************/

/********************************************************************
 ***	All definitions are for Primary Rate device unless noted.
 ********************************************************************/

/********************************************************************
 ***	Status register bit assignments.
 ********************************************************************/

#ifndef	VMO
#ifndef BIOS
typedef unsigned char uchar;
#define	VMO(t,a)	(*((volatile t *) a))
#endif
#endif

#define	INT_SW0		0x0100		/* Software interrupt 0 */
#define	INT_SW1		0x0200		/* Software interrupt 1 */
#define	INT_HW0		0x0400		/* Hardware interrupt 0 */
#define	INT_HW1		0x0800		/* Hardware interrupt 1 */
#define	INT_HW2		0x1000		/* Hardware interrupt 2 */
#define	INT_HW3		0x2000		/* Hardware interrupt 3 */
#define	INT_HW4		0x4000		/* Hardware interrupt 4 */
#define	INT_HW5		0x4000		/* Hardware interrupt 5 */
#define	INT_HW6		0x8000		/* Hardware interrupt 6 */

#define	SR_SOFT		(INT_SW0|INT_SW1)/* Software interrupt */
#define	SR_TIMER	INT_HW0		/* Timer interrupt */
#define	SR_HOST		INT_HW1		/* HOST interrupt */
#define	SR_MUNICH	INT_HW2		/* Munich interrupt */
#define	SR_PAC		INT_HW3		/* PAC interrupt */
#define	SR_PRISM	INT_HW4		/* PRISM interrupt */
#define	SR_HAWAII	INT_HW5		/* HAWAII interrupt */
#define	SR_STAC		INT_HW6		/* STAC interrupt */

/********************************************************************
 ***	Miscellaneous device locations
 ********************************************************************/

#if PRI
#define	GPP0 		VMO(uchar, 0xa2000000)
#define	GP_HDI		0x01			/* Hawaii Data In */
#define	GP_HDO		0x01			/* Hawaii Data Out */
#define	GP_HSCK		0x02			/* Hawaii Data Clock */
#define	GP_HCS0		0x04			/* Hawaii CS 0 */
#define	GP_HCS1		0x08			/* Hawaii CS 1 */

#define	GP_MUN0LOOP	0x10			/* Munich 0, RSP/TSP aligned for loopback */
#define	GP_MUN1LOOP	0x20			/* Munich 1, RSP/TSP aligned for loopback */
#define	GP_PCMCLK	0x40			/* Enable PCM Hwy clocks */
#define	GP_STAC_MISSING	0x02			/* STAC 9706 presence (AL) */
#define	GP_TWO_CHANNELS	0x04			/* 2 Physical Channels (AH) */
#define	GP_NO_DAI	0x08			/* Drop & Insert (AL) */
#define	GP_T1_CARD	0x10			/* T1 Card (vs. E1) (AH) */

#define	GPP1 		VMO(uchar, 0xa2000008)
#define	GP_MUNRES1	0x80			/* Reset Munich 1 */
#define	GP_MUNRES0	0x40			/* Reset Munich 0 */
#define	GP_DI		0x20			/* Drop & Insert Mode */
#define	GP_C1E1		0x10			/* Channel 1, E1 Mode */
#define	GP_C0E1		0x08			/* Channel 0, E1 Mode */
#define	GP_C1M		0x04			/* Channel 1, Master  */
#define	GP_C0M		0x02			/* Channel 0, Master  */
#define	GP_IHOST	0x01			/* Interrupt Host     */

#define	GPP2		VMO(uchar, 0xa2010000)

#define	GPP3		VMO(uchar, 0xa2010008)

#define	PAC_0		VMO(pac_ctrl_t, 0xa2020000)
#define	PAC_1		VMO(pac_ctrl_t, 0xa2030000)

#define INTERRUPT	VMO(uchar, 0xa2040000)
#define	ACK_HOSTINT	0x02
#define	ACK_TIMERINT	0x01

#else

#define	GPP0		VMO(unsigned short, 0xa2050000)
#define	HINTR		0x01
#define	L1_232		0x02
#define	L2_232		0x04
#define	L1_M		0x08
#define	L2_M		0x10
#define	L1_485		0x20
#define	L2_485		0x40
#define	REFSEL		0x80
#define	TENM1		0x100
#define	TENM2		0x200
#define	XRC1		0x400
#define	XRC2		0x800

#define INTERRUPT	VMO(uchar, 0xa2060000)

#define	X25_CTRL_PORT	VMO(uchar, 0xa2070000)
#define	DTR_1		0x01
#define	DTR_2		0x02
#define	DSR_1		0x01
#define	DSR_2		0x02
#if PCI
/* These items apply to PCI Syncport cards only */
#define	V11_1		0x00
#define	V24_1		0x10
#define	V35_1		0x04
#define	V11_2		0x00
#define	V24_2		0x20
#define	V35_2		0x08
#endif	/* PCI */

#endif	/* PRI */

#define INTACK		INTERRUPT

/*
 * The interrupt register serves to both identify sources of interrupts,
 * and acknowledge the host & timer interrupts. The bits are used as
 * follows:
 *
 * Bit		7	6	5	4	3	2	1	0
 * ============================================================================
 * Write	x	x	x	x	x	x    HOSTACK  TIMERACK
 *
 * Read	       STAC   PRISM    HAW1    HAW0    PAC1    PAC0    MUN1    MUN0
 */
#ifdef LANGUAGE_ASSEMBLY
#define TIMERACK	sb	$1, INTACK
#define HOSTACK		sb	$2, INTACK
#else
#define TIMERACK	INTACK = 1
#define HOSTACK		INTACK = 2
#endif

#ifdef PRI
#define	TIMER		VMO(TM, 0xa2050000)
#else
#define	TIMER		VMO(TM, 0xa2040000)
#endif
#define	UART		VMO(uchar, 0xa2060000)
#define	PRISM		VMO(uchar, 0xa2080000)
#define	MUNICH_0	VMO(uchar, 0xa2070000)
#define	MUNICH_1	VMO(uchar, 0xa2070008)
#define	STAC		VMO(STAC9706, 0xa20c0000)

#define	CPU_HZ		20000000		/* clock rate of CPU */

#define	TICRATE		1000			/* clock interrupt rate */

#define	MUNICH_CSA_0	VMO(uint, 0xa03ffffc)
#define	MUNICH_CSA_1	VMO(uint, 0xa03ffff8)
