/***********************************

 * $Id: quicc.h,v 1.5 1997/08/27 20:55:09 gary Exp $

 ***********************************

 *

 ***************************************

 * Definitions of QUICC memory structures

 ***************************************

 */



#ifndef __QUICC_H

#define __QUICC_H



/*

 * include registers and

 * parameter ram definitions files

 */

#include "regs.h"

#include "pram.h"





/* Buffer Descriptors */

typedef struct

{

    volatile unsigned short     status;

    volatile unsigned short     length;

    volatile unsigned char      *buf;

} BD;



/* User data (BD's) or microcode area */

struct user_data

{

    /* DPR BASE + 0x000: user data memory */

    volatile unsigned char udata_bd_ucode1[0x200]; /* user BD's or Ucode 1    */

    volatile unsigned char udata_bd_ucode2[0x200]; /* user BD's or Ucode 2    */

    volatile unsigned char udata_bd_ucode3[0x400]; /* user BD's or Ucode 3    */

    volatile unsigned char udata_bd[0x600];        /* user BD's               */

    volatile unsigned char ucode_ext3[0x100];      /* Ucode 2 extention       */

    volatile unsigned char ucode_ext12[0x100];     /* Ucode 1 and 2 extention */

    volatile unsigned char RESERVED1[0xc00];       /* Reserved area           */

};

/* Buffer descriptor rings and other information */

typedef struct LOCAL_DATA {
	/* Transmit data ring buffer descriptors */
	BD TxRing[NUM_CHANNELS][NUM_QUICC_TX_ELEMENTS] ;

	/*
	 * Index to the "head" of the TxRing (i.e. the next
	 * idle Tx Buffer Descriptor for a given channel).
	 * Note that the shared tx ring's tail is also,
	 * by virtue of its function, the "tail" of the
	 * TxRing.
	 */
	unsigned long TxHead[NUM_CHANNELS] ;

	/* Receive data ring buffer descriptors */
	BD RxRing[NUM_CHANNELS][NUM_QUICC_RX_ELEMENTS] ;

	/*
	 * Index to the local "tail" of the RxRing (i.e. the
	 * next buffer slot that will be refreshed).  This
	 * also marks the "dead slot" that is required to prevent
	 * a wrap-around during a burst condition.
	 */
	unsigned long RxTail[NUM_CHANNELS] ;

	/*
	 * Booleans which determine whether or not we poll
	 * the shared receive ring for new buffers
	 */
	unsigned long RxPollMode[NUM_CHANNELS] ;

	/* Half Duplex Polling of modem signals */
	unsigned long HdpxPoll[NUM_CHANNELS]; 
	unsigned long HdpxPollMask ;

	/* Pointers to the shared transmit ring structures */
	volatile quicc_tx_channel_t *Tx_Pointers[NUM_CHANNELS] ;

	/* Pointers to the shared receive ring structures */
	volatile quicc_rx_channel_t *Rx_Pointers[NUM_CHANNELS] ;

	/* Local Cable ID values */
	volatile unsigned char Cable_ID[NUM_CHANNELS] ;

	/* Pointer to shared Cable ID array */
	volatile unsigned char *Shared_Cable_ID ;

	/* Local copy of modem signal state */
	volatile unsigned char ModemSignals[NUM_CHANNELS] ;

	/* Shared copy of modem signal state */
	volatile unsigned char *SharedModemSignals ;

	/* Mask which indicates port pin to read for line's CD status */
	unsigned long CDMask[NUM_CHANNELS] ;

	/* Mask which indicates port pin to read for line's CTS status */
	unsigned long CTSMask[NUM_CHANNELS] ;

	/* Mask which indicates port pin to read for line's DSR status */
	unsigned long DSRMask[NUM_CHANNELS] ;

	/* Mask which indicates port pin to read for line's RI status */
	unsigned long RIMask[NUM_CHANNELS] ;

	/* Mask which indicates port pin to read for line's Mode status */
	unsigned long ModeMask[NUM_CHANNELS] ;

	/* Pointer to the shared command queue */
	volatile quicc_cmd_queue_t *Command_Queue ;

	/* Pointer to the array of shared data buffers */
	volatile scc_parm_t *Shared_Structure ;

	/* Pointer to shared timer counter */
	volatile unsigned long *Shared_Timer ;

	/* Local copy of timer value */
	unsigned long Local_Timer ;

	/* Port B Shadow Register */
	unsigned long PortBShadowRegister ;

	/* Port D Shadow Register */
	unsigned long PortDShadowRegister ;

	//BD SMCTxRing[2][2] ;
	//BD SMCRxRing[2][2] ;

	unsigned short Last_Line_Speed_Read[4] ;
	unsigned long *SharedLineSpeed ;
	unsigned long *SharedPortStatus ;
	unsigned long *SharedRxGlitch ;
	unsigned long *SharedTxGlitch ;
	unsigned long *SharedRxPacketDisfc ;


} local_data_t ;


/*

 * internal ram

 */

typedef struct quicc

{

/* BASE + 0x0000: INTERNAL REGISTERS */

/* SIU */

    volatile unsigned long  siu_mcr;        /* module configuration reg */

    volatile unsigned long  siu_sypcr;      /* System protection cnt */

    volatile unsigned char  RESERVED58[0x6];

    volatile unsigned short siu_swsr;       /* sw service */

    volatile unsigned long  siu_sipend;     /* Interrupt pend reg */

    volatile unsigned long  siu_simask;     /* Interrupt mask reg */

    volatile unsigned long  siu_siel;       /* Interrupt edge level mask reg */

    volatile unsigned long  siu_sivec;      /* Interrupt vector */

    volatile unsigned long  siu_tesr;       /* Transfer error status */

    volatile unsigned char  RESERVED1[0xc];

    volatile unsigned long  sdma_sdcr;      /* SDMA configuration reg */

    volatile unsigned char  RESERVED55[0x4c];

/* PCMCIA */

    volatile unsigned long  pcmcia_pbr0;    /* Interface Base Register 0 */

    volatile unsigned long  pcmcia_por0;    /* Interface Option Register 0 */

    volatile unsigned long  pcmcia_pbr1;    /* Interface Base Register 1 */

    volatile unsigned long  pcmcia_por1;    /* Interface Option Register 1 */

    volatile unsigned long  pcmcia_pbr2;    /* Interface Base Register 2 */

    volatile unsigned long  pcmcia_por2;    /* Interface Option Register 2 */

    volatile unsigned long  pcmcia_pbr3;    /* Interface Base Register 3 */

    volatile unsigned long  pcmcia_por3;    /* Interface Option Register 3 */

    volatile unsigned long  pcmcia_pbr4;    /* Interface Base Register 4 */

    volatile unsigned long  pcmcia_por4;    /* Interface Option Register 4 */

    volatile unsigned long  pcmcia_pbr5;    /* Interface Base Register 5 */

    volatile unsigned long  pcmcia_por5;    /* Interface Option Register 5 */

    volatile unsigned long  pcmcia_pbr6;    /* Interface Base Register 6 */

    volatile unsigned long  pcmcia_por6;    /* Interface Option Register 6 */

    volatile unsigned long  pcmcia_pbr7;    /* Interface Base Register 7 */

    volatile unsigned long  pcmcia_por7;    /* Interface Option Register 7 */

    volatile unsigned char  RESERVED68[0x20];

    volatile unsigned long  pcmcia_pgcra;   /* Interface General Control A */

    volatile unsigned long  pcmcia_pgcrb;   /* Interface General Control B */

    volatile unsigned long  pcmcia_pscr;    /* Interface Status Changed Reg */

    volatile unsigned char  RESERVED69[0x4];

    volatile unsigned long  pcmcia_pipr;    /* Interface Input Pins Register */

    volatile unsigned char  RESERVED70[0x4];

    volatile unsigned long  pcmcia_per;     /* Interface Enable Register */

    volatile unsigned char  RESERVED2[0x4];

/* MEMC */

    volatile unsigned long  memc_br0;       /* base register 0   */

    volatile unsigned long  memc_or0;       /* option register 0 */

    volatile unsigned long  memc_br1;       /* base register 1   */

    volatile unsigned long  memc_or1;       /* option register 1 */

    volatile unsigned long  memc_br2;       /* base register 2   */

    volatile unsigned long  memc_or2;       /* option register 2 */

    volatile unsigned long  memc_br3;       /* base register 3   */

    volatile unsigned long  memc_or3;       /* option register 3 */

    volatile unsigned long  memc_br4;       /* base register 3   */

    volatile unsigned long  memc_or4;       /* option register 3 */

    volatile unsigned long  memc_br5;       /* base register 3   */

    volatile unsigned long  memc_or5;       /* option register 3 */

    volatile unsigned long  memc_br6;       /* base register 3   */

    volatile unsigned long  memc_or6;       /* option register 3 */

    volatile unsigned long  memc_br7;       /* base register 3   */

    volatile unsigned long  memc_or7;       /* option register 3 */

    volatile unsigned char  RESERVED3[0x24];

    volatile unsigned long  memc_mar;       /* Memory address */

    volatile unsigned long  memc_mcr;       /* Memory command */

    volatile unsigned char  RESERVED4[0x4];

    volatile unsigned long  memc_mamr;      /* Machine A mode */

    volatile unsigned long  memc_mbmr;      /* Machine B mode */

    volatile unsigned short memc_mstat;     /* Memory status */

    volatile unsigned short memc_mptpr;     /* Memory periodic timer prescalar */

    volatile unsigned long  memc_mdr;       /* Memory data */

    volatile unsigned char  RESERVED5[0x80];

/* SYSTEM INTEGRATION TIMERS */

    volatile unsigned short simt_tbscr;     /* Time base stat&ctr */ 

	volatile unsigned short SPECIALRESV42199 ; /* Reserve */

    volatile unsigned long  simt_tbreff0;   /* Time base reference 0 */

    volatile unsigned long  simt_tbreff1;   /* Time base reference 1 */

    volatile unsigned char  RESERVED6[0x14];

    volatile unsigned short  simt_rtcsc;     /* Realtime clk stat&cntr 1 */

	volatile unsigned short SPECIALRESV421992 ; /* Reserved */

    volatile unsigned long  simt_rtc;       /* Realtime clock */

    volatile unsigned long  simt_rtsec;     /* Realtime alarm seconds */

    volatile unsigned long  simt_rtcal;     /* Realtime alarm */

    volatile unsigned char  RESERVED56[0x10];

    volatile unsigned short  simt_piscr;     /* PIT stat&ctrl */

	volatile unsigned char  RESERVEDCDK1[2] ;

    volatile unsigned long  simt_pitc;      /* PIT counter */

    volatile unsigned long  simt_pitr;      /* PIT */

    volatile unsigned char  RESERVED7[0x34];

/* CLOCKS, RESET */

    volatile unsigned long  clkr_sccr;      /* System clk cntrl */

    volatile unsigned long  clkr_plprcr;    /* PLL reset&ctrl */

    volatile unsigned long  clkr_rsr;       /* reset status */

    volatile unsigned char  RESERVED8[0x574];

/* LCD */

    volatile unsigned short lcd_lcolr[16];/* lcd color Ram */

    volatile unsigned char  RESERVED66[0x20];

    volatile unsigned long  lcd_lccr;       /* configuration Reg */

    volatile unsigned long  lcd_lchcr;      /* Horizontal ctl Reg */

    volatile unsigned long  lcd_lcvcr;      /* Vertical ctl Reg */

    volatile unsigned char  RESERVED67[4];

    volatile unsigned long  lcd_lcfaa;      /* Frame buffer A Address */

    volatile unsigned long  lcd_lcfba;      /* Frame buffer B Address */

    volatile unsigned char  lcd_lcsr;       /* Status Reg */

    volatile unsigned char  RESERVED9[0x7];

/* I2C */

    volatile unsigned char  i2c_i2mod;      /* i2c mode */

    volatile unsigned char  RESERVED59[3];

    volatile unsigned char  i2c_i2add;      /* i2c address */

    volatile unsigned char  RESERVED60[3];

    volatile unsigned char  i2c_i2brg;      /* i2c brg */

    volatile unsigned char  RESERVED61[3];

    volatile unsigned char  i2c_i2com;      /* i2c command */

    volatile unsigned char  RESERVED62[3];

    volatile unsigned char  i2c_i2cer;      /* i2c event */

    volatile unsigned char  RESERVED63[3];

    volatile unsigned char  i2c_i2cmr;      /* i2c mask */

    volatile unsigned char  RESERVED10[0x8b];

/* DMA */

    volatile unsigned char  RESERVED11[0x4];

    volatile unsigned long  dma_sdar;       /* SDMA address reg */

    volatile unsigned char  RESERVED12[0x2];

    volatile unsigned char  dma_sdsr;       /* SDMA status reg */

    volatile unsigned char  RESERVED13[0x3];

    volatile unsigned char  dma_sdmr;       /* SDMA mask reg */

    volatile unsigned char  RESERVED14[0x1];

    volatile unsigned char  dma_idsr1;      /* IDMA1 status reg */

    volatile unsigned char  RESERVED15[0x3];

    volatile unsigned char  dma_idmr1;      /* IDMA1 mask reg */

    volatile unsigned char  RESERVED16[0x3];

    volatile unsigned char  dma_idsr2;      /* IDMA2 status reg */

    volatile unsigned char  RESERVED17[0x3];

    volatile unsigned char  dma_idmr2;      /* IDMA2 mask reg */

    volatile unsigned char  RESERVED18[0x13];

/* CPM Interrupt Controller */

    volatile unsigned short cpmi_civr;      /* CP interrupt vector reg */

    volatile unsigned char  RESERVED19[0xe];

    volatile unsigned long  cpmi_cicr;      /* CP interrupt configuration reg */

    volatile unsigned long  cpmi_cipr;      /* CP interrupt pending reg */

    volatile unsigned long  cpmi_cimr;      /* CP interrupt mask reg */

    volatile unsigned long  cpmi_cisr;      /* CP interrupt in-service reg */

/* I/O port */

    volatile unsigned short pio_padir;      /* port A data direction reg */

    volatile unsigned short pio_papar;      /* port A pin assignment reg */

    volatile unsigned short pio_paodr;      /* port A open drain reg */

    volatile unsigned short pio_padat;      /* port A data register */

    volatile unsigned char  RESERVED20[0x8];

    volatile unsigned short pio_pcdir;      /* port C data direction reg */

    volatile unsigned short pio_pcpar;      /* port C pin assignment reg */

    volatile unsigned short pio_pcso;       /* port C special options */

    volatile unsigned short pio_pcdat;      /* port C data register */

    volatile unsigned short pio_pcint;      /* port C interrupt cntrl reg */

    volatile unsigned char  RESERVED64[6];

    volatile unsigned short pio_pddir;      /* port D Data Direction reg */

    volatile unsigned short pio_pdpar;      /* port D pin assignment reg */

    volatile unsigned char  RESERVED65[2];

    volatile unsigned short pio_pddat;      /* port D data reg */

    volatile unsigned char  RESERVED21[0x8];

/* CPM Timer */

    volatile unsigned short timer_tgcr;     /* timer global configuration  reg */

    volatile unsigned char  RESERVED22[0xe];

    volatile unsigned short timer_tmr1;     /* timer 1 mode reg */

    volatile unsigned short timer_tmr2;     /* timer 2 mode reg */

    volatile unsigned short timer_trr1;     /* timer 1 referance reg */

    volatile unsigned short timer_trr2;     /* timer 2 referance reg */

    volatile unsigned short timer_tcr1;     /* timer 1 capture reg */

    volatile unsigned short timer_tcr2;     /* timer 2 capture reg */

    volatile unsigned short timer_tcn1;     /* timer 1 counter reg */

    volatile unsigned short timer_tcn2;     /* timer 2 counter reg */

    volatile unsigned short timer_tmr3;     /* timer 3 mode reg */

    volatile unsigned short timer_tmr4;     /* timer 4 mode reg */

    volatile unsigned short timer_trr3;     /* timer 3 referance reg */

    volatile unsigned short timer_trr4;     /* timer 4 referance reg */

    volatile unsigned short timer_tcr3;     /* timer 3 capture reg */

    volatile unsigned short timer_tcr4;     /* timer 4 capture reg */

    volatile unsigned short timer_tcn3;     /* timer 3 counter reg */

    volatile unsigned short timer_tcn4;     /* timer 4 counter reg */

    volatile unsigned short timer_ter1;     /* timer 1 event reg */

    volatile unsigned short timer_ter2;     /* timer 2 event reg */

    volatile unsigned short timer_ter3;     /* timer 3 event reg */

    volatile unsigned short timer_ter4;     /* timer 4 event reg */

    volatile unsigned char  RESERVED23[0x8];

/* CP */

    volatile unsigned short cp_cr;          /* command register */

    volatile unsigned char  RESERVED24[0x2];

    volatile unsigned short cp_rccr;        /* main configuration reg */

    volatile unsigned char  RESERVED25;

    volatile unsigned char  cp_rmds;        /* development support status reg */

    volatile unsigned long  cp_rmdr;        /* development support control reg */

    volatile unsigned short cp_rctr1;       /* ram break register 1 */

    volatile unsigned short cp_rctr2;       /* ram break register 2 */

    volatile unsigned short cp_rctr3;       /* ram break register 3 */

    volatile unsigned short cp_rctr4;       /* ram break register 4 */

    volatile unsigned char  RESERVED26[0x2];

    volatile unsigned short cp_rter;        /* RISC timers event reg */

    volatile unsigned char  RESERVED27[0x2];

    volatile unsigned short cp_rtmr;        /* RISC timers mask reg */

    volatile unsigned char  RESERVED28[0x14];

/* BRG */

    union 

    {

        volatile unsigned long l;

        struct 

        {

            volatile unsigned short BRGC_RESERV:14;

            volatile unsigned short rst:1;

            volatile unsigned short en:1;

            volatile unsigned short extc:2;

            volatile unsigned short atb:1;

            volatile unsigned short cd:12;

            volatile unsigned short div16:1;

        } b;

    } brgc[4];

/* SCC registers */

    struct scc_regs 

    {

        union 

        {

            struct 

            {

                /* Low word. */

                volatile unsigned short GSMR_RESERV2:1;

                volatile unsigned short edge:2;

                volatile unsigned short tci:1;

                volatile unsigned short tsnc:2;

                volatile unsigned short rinv:1;

                volatile unsigned short tinv:1;

                volatile unsigned short tpl:3;

                volatile unsigned short tpp:2;

                volatile unsigned short tend:1;

                volatile unsigned short tdcr:2;

                volatile unsigned short rdcr:2;

                volatile unsigned short renc:3;

                volatile unsigned short tenc:3;

                volatile unsigned short diag:2;

                volatile unsigned short enr:1;

                volatile unsigned short ent:1;

                volatile unsigned short mode:4;

                /* High word. */

                volatile unsigned short GSMR_RESERV1:14;

                volatile unsigned short pri:1;

                volatile unsigned short gde:1;

                volatile unsigned short tcrc:2;

                volatile unsigned short revd:1;

                volatile unsigned short trx:1;

                volatile unsigned short ttx:1;

                volatile unsigned short cdp:1;

                volatile unsigned short ctsp:1;

                volatile unsigned short cds:1;

                volatile unsigned short ctss:1;

                volatile unsigned short tfl:1;

                volatile unsigned short rfw:1;

                volatile unsigned short txsy:1;

                volatile unsigned short synl:2;

                volatile unsigned short rtsm:1;

                volatile unsigned short rsyn:1;

            } b;

            struct 

            {

                volatile unsigned long low;

                volatile unsigned long high;

            } w;

        } scc_gsmr;                         /* SCC general mode reg            */

        volatile unsigned short scc_psmr;   /* protocol specific mode register */

        volatile unsigned char  RESERVED29[0x2];

        volatile unsigned short scc_todr;   /* SCC transmit on demand */

        volatile unsigned short scc_dsr;        /* SCC data sync reg */

        volatile unsigned short scc_scce;       /* SCC event reg */

        volatile unsigned char  RESERVED30[0x2];

        volatile unsigned short scc_sccm;       /* SCC mask reg */

        volatile unsigned char  RESERVED31[0x1];

        volatile unsigned char  scc_sccs;       /* SCC status reg */

        volatile unsigned char  RESERVED32[0x8];

    } scc_regs[4];

/* SMC */

    struct smc_regs 

    {

        volatile unsigned char  RESERVED34[0x2];

        volatile unsigned short smc_smcmr;      /* SMC mode reg */

        volatile unsigned char  RESERVED35[0x2];

        volatile unsigned char  smc_smce;       /* SMC event reg */

        volatile unsigned char  RESERVED36[0x3];

        volatile unsigned char  smc_smcm;       /* SMC mask reg */

        volatile unsigned char  RESERVED37[0x5];

    } smc_regs[2];

/* SPI */

    volatile unsigned short spi_spmode;     /* SPI mode reg */

    volatile unsigned char  RESERVED38[0x4];

    volatile unsigned char  spi_spie;       /* SPI event reg */

    volatile unsigned char  RESERVED39[0x3];

    volatile unsigned char  spi_spim;       /* SPI mask reg */

    volatile unsigned char  RESERVED40[0x2];

    volatile unsigned char  spi_spcom;      /* SPI command reg */

    volatile unsigned char  RESERVED41[0x4];

/* PIP */

    volatile unsigned short pip_pipc;       /* pip configuration reg */

    volatile unsigned char  RESERVED42[0x2];

    volatile unsigned short pip_ptpr;       /* pip timing parameters reg */

    volatile unsigned long  pip_pbdir;      /* port b data direction reg */

    volatile unsigned long  pip_pbpar;      /* port b pin assignment reg */

    volatile unsigned char  RESERVED43[0x2];

    volatile unsigned short pip_pbodr;      /* port b open drain reg */

    volatile unsigned long  pip_pbdat;      /* port b data reg */

    volatile unsigned char  RESERVED44[0x18];

/* Serial Interface */

    volatile unsigned long  si_simode;      /* SI mode register */

    volatile unsigned char  si_sigmr;       /* SI global mode register */

    volatile unsigned char  RESERVED45;

    volatile unsigned char  si_sistr;       /* SI status register */

    volatile unsigned char  si_sicmr;       /* SI command register */

    volatile unsigned char  RESERVED46[0x4];

    volatile unsigned long  si_sicr;        /* SI clock routing */

    volatile unsigned long  si_sirp;        /* SI ram pointers */

    volatile unsigned char  RESERVED47[0x10c];

    volatile unsigned char  si_siram[0x200]; /* SI routing ram */

    volatile unsigned char  RESERVED48[0x1200];



/* BASE + 0x2000: (start of DPR) user BD's/microcode/QMC memory */

    union 

    {

        struct qmc_pram  ch_pram_tbl[64]; /* 64*64(bytes) per channel */

        struct user_data u;

	local_data_t local_data ;

    } ch_or_u;       /* multichannel pram or user space */



/* BASE + 0x3c00: PARAMETER RAM */

    union 

    {

        struct scc_pram

        {

            union

            {

                struct hdlc_pram        h;

                struct uart_pram        u;

                struct bisync_pram      b;

                struct transparent_pram t;

                struct async_hdlc_pram  a;

                unsigned char           RESERVED50[0x80];

            } pscc;         /* scc protocol dependent parameters */

            union 

            {

                struct

                {

                    struct i2c_pram     i2c;

                    unsigned char       RESERVED56[0x18];

                    struct idma_pram    idma1;

                } i2c_idma;

                struct

                {

                    struct spi_pram     spi;

                    unsigned char       RESERVED57[0x8];

                    struct timer_pram   timer;

                    struct idma_pram    idma2;

                } spi_timer_idma;

                struct 

                {

                    union {

                        struct smc_uart_pram   u;

                        struct smc_trnsp_pram  t;

                        struct centronics_pram c;

                    } psmc;

                    unsigned char   modem_param[0x40];

                } smc_modem;

                struct 

                {

                    unsigned char   RESERVED54[0x40];

                    struct ucode_pram       ucode;

                } pucode;

            } pothers;

        } scc;

        struct ethernet_pram     enet_scc;

        struct global_multi_pram m;

        unsigned char            pr[0x100];

    } pram[4];

} QUICC;

/* Port A/B/C/D Pin Assignments */
#define	PA15		0x0001
#define	PA14		0x0002
#define	PA13		0x0004
#define	PA12		0x0008
#define	PA11		0x0010
#define	PA10		0x0020
#define	PA9		0x0040
#define	PA8		0x0080
#define	PA7		0x0100
#define	PA6		0x0200
#define	PA5		0x0400
#define	PA4		0x0800
#define	PA3		0x1000
#define	PA2		0x2000
#define	PA1		0x4000
#define	PA0		0x8000
#define	PB31		0x00001L
#define	PB30		0x00002L
#define	PB29		0x00004L
#define	PB28		0x00008L
#define	PB27		0x00010L
#define	PB26		0x00020L
#define	PB25		0x00040L
#define	PB24		0x00080L
#define	PB23		0x00100L
#define	PB22		0x00200L
#define	PB21		0x00400L
#define	PB20		0x00800L
#define	PB19		0x01000L
#define	PB18		0x02000L
#define	PB17		0x04000L
#define	PB16		0x08000L
#define	PB15		0x10000L
#define	PB14		0x20000L
#define	PC15		0x0001
#define	PC14		0x0002
#define	PC13		0x0004
#define	PC12		0x0008
#define	PC11		0x0010
#define	PC10		0x0020
#define	PC9		0x0040
#define	PC8		0x0080
#define	PC7		0x0100
#define	PC6		0x0200
#define	PC5		0x0400
#define	PC4		0x0800
#define	PD15		0x0001
#define	PD14		0x0002
#define	PD13		0x0004
#define	PD12		0x0008
#define	PD11		0x0010
#define	PD10		0x0020
#define	PD9		0x0040
#define	PD8		0x0080
#define	PD7		0x0100
#define	PD6		0x0200
#define	PD5		0x0400
#define	PD4		0x0800
#define	PD3		0x1000

#define	CPMI_PC15	0x80000000
#define	CPMI_SCC1	0x40000000
#define	CPMI_SCC2	0x20000000
#define	CPMI_SCC3	0x10000000
#define	CPMI_SCC4	0x08000000


#define	SIU_SIEL_ED0		0x80000000
#define	SIU_SIEL_WM0		0x40000000
#define	SIU_SIEL_ED1		0x20000000
#define	SIU_SIEL_WM1		0x10000000
#define	SIU_SIEL_ED2		0x08000000
#define	SIU_SIEL_WM2		0x04000000
#define	SIU_SIEL_ED3		0x02000000
#define	SIU_SIEL_WM3		0x01000000
#define	SIU_SIEL_ED4		0x00800000
#define	SIU_SIEL_WM4		0x00400000
#define	SIU_SIEL_ED5		0x00200000
#define	SIU_SIEL_WM5		0x00100000
#define	SIU_SIEL_ED6		0x00080000
#define	SIU_SIEL_WM6		0x00040000
#define	SIU_SIEL_ED7		0x00020000
#define	SIU_SIEL_WM7		0x00010000


#define	SIU_SIPEND_IRQ0		0x80000000
#define	SIU_SIPEND_LVL0		0x40000000
#define	SIU_SIPEND_IRQ1		0x20000000
#define	SIU_SIPEND_LVL1		0x10000000
#define	SIU_SIPEND_IRQ2		0x08000000
#define	SIU_SIPEND_LVL2		0x04000000
#define	SIU_SIPEND_IRQ3		0x02000000
#define	SIU_SIPEND_LVL3		0x01000000
#define	SIU_SIPEND_IRQ4		0x00800000
#define	SIU_SIPEND_LVL4		0x00400000
#define	SIU_SIPEND_IRQ5		0x00200000
#define SIU_SIPEND_LVL5		0x00100000
#define	SIU_SIPEND_IRQ6		0x00080000
#define SIU_SIPEND_LVL6		0x00040000
#define SIU_SIPEND_IRQ7		0x00020000
#define	SIU_SIPEND_LVL7		0x00010000

#define	SIU_SIMASK_IMR0		0x80000000
#define	SIU_SIMASK_LVM0		0x40000000
#define	SIU_SIMASK_IMR1		0x20000000
#define	SIU_SIMASK_LVM1		0x10000000
#define	SIU_SIMASK_IMR2		0x08000000
#define	SIU_SIMASK_LVM2		0x04000000
#define	SIU_SIMASK_IMR3		0x02000000
#define	SIU_SIMASK_LVM3		0x01000000
#define	SIU_SIMASK_IMR4		0x00800000
#define	SIU_SIMASK_LVM4		0x00400000
#define	SIU_SIMASK_IMR5		0x00200000
#define	SIU_SIMASK_LVM5		0x00100000
#define	SIU_SIMASK_IMR6		0x00080000
#define	SIU_SIMASK_LVM6		0x00040000
#define	SIU_SIMASK_IMR7		0x00020000
#define	SIU_SIMASK_LVM7		0x00010000




/* SICR Settings */
#define	SCC1_RX_BRG1	0x00000000
#define	SCC1_RX_BRG2	0x00000008
#define	SCC1_RX_BRG3	0x00000010
#define	SCC1_RX_BRG4	0x00000018
#define	SCC1_RX_CLK1	0x00000020
#define	SCC1_RX_CLK2	0x00000028
#define	SCC1_RX_CLK3	0x00000030
#define	SCC1_RX_CLK4	0x00000038
#define	SCC2_RX_BRG1	0x00000000
#define	SCC2_RX_BRG2	0x00000800
#define	SCC2_RX_BRG3	0x00001000
#define	SCC2_RX_BRG4	0x00001800
#define	SCC2_RX_CLK1	0x00002000
#define	SCC2_RX_CLK2	0x00002800
#define	SCC2_RX_CLK3	0x00003000
#define	SCC2_RX_CLK4	0x00003800
#define	SCC3_RX_BRG1	0x00000000
#define	SCC3_RX_BRG2	0x00080000
#define	SCC3_RX_BRG3	0x00100000
#define	SCC3_RX_BRG4	0x00180000
#define	SCC3_RX_CLK5	0x00200000
#define	SCC3_RX_CLK6	0x00280000
#define	SCC3_RX_CLK7	0x00300000
#define	SCC3_RX_CLK8	0x00380000
#define	SCC4_RX_BRG1	0x00000000
#define	SCC4_RX_BRG2	0x08000000
#define	SCC4_RX_BRG3	0x10000000
#define	SCC4_RX_BRG4	0x18000000
#define	SCC4_RX_CLK5	0x20000000
#define	SCC4_RX_CLK6	0x28000000
#define	SCC4_RX_CLK7	0x30000000
#define	SCC4_RX_CLK8	0x38000000
#define	SCC1_TX_BRG1	0x00000000
#define	SCC1_TX_BRG2	0x00000001
#define	SCC1_TX_BRG3	0x00000002
#define	SCC1_TX_BRG4	0x00000003
#define	SCC1_TX_CLK1	0x00000004
#define	SCC1_TX_CLK2	0x00000005
#define	SCC1_TX_CLK3	0x00000006
#define	SCC1_TX_CLK4	0x00000007
#define	SCC2_TX_BRG1	0x00000000
#define	SCC2_TX_BRG2	0x00000100
#define	SCC2_TX_BRG3	0x00000200
#define	SCC2_TX_BRG4	0x00000300
#define	SCC2_TX_CLK1	0x00000400
#define	SCC2_TX_CLK2	0x00000500
#define	SCC2_TX_CLK3	0x00000600
#define	SCC2_TX_CLK4	0x00000700
#define	SCC3_TX_BRG1	0x00000000
#define	SCC3_TX_BRG2	0x00010000
#define	SCC3_TX_BRG3	0x00020000
#define	SCC3_TX_BRG4	0x00030000
#define	SCC3_TX_CLK5	0x00040000
#define	SCC3_TX_CLK6	0x00050000
#define	SCC3_TX_CLK7	0x00060000
#define	SCC3_TX_CLK8	0x00070000
#define	SCC4_TX_BRG1	0x00000000
#define	SCC4_TX_BRG2	0x01000000
#define	SCC4_TX_BRG3	0x02000000
#define	SCC4_TX_BRG4	0x03000000
#define	SCC4_TX_CLK5	0x04000000
#define	SCC4_TX_CLK6	0x05000000
#define	SCC4_TX_CLK7	0x06000000
#define	SCC4_TX_CLK8	0x07000000

#define	TXBD_READY	0x8000
#define	TXBD_WRAP	0x2000
#define	TXBD_INTERRUPT	0x1000
#define	TXBD_LAST	0x0800
#define	TXBD_TXCRC	0x0400
#define	TXBD_CMODE	0x0200
/* PREAMBLE???  NO STOP BIT???  The manual fails to define these */
#define	TXBD_UNDERRUN	0x0002
#define	TXBD_CTSLOST	0x0001
#define	TXBD_ERRS	(TXBD_UNDERRUN|TXBD_CTSLOST)

#define	RXBD_EMPTY	0x8000
#define	RXBD_WRAP	0x2000
#define	RXBD_INTERRUPT	0x1000
#define	RXBD_LAST	0x0800
#define	RXBD_FIRST	0x0400
#define	RXBD_CMODE	0x0200
#define	RXBD_DE		0x0080
#define	RXBD_LG		0x0020
#define	RXBD_NO		0x0010
#define	RXBD_AB		0x0008
#define	RXBD_CR		0x0004
#define	RXBD_OV		0x0002
#define	RXBD_CD		0x0001
#define	RXBD_ERRS	\
	(RXBD_DE|RXBD_LG|RXBD_NO|RXBD_AB|RXBD_CR|RXBD_OV|RXBD_CD)

#define	BRGC_EN		0x00010000
#define	BRGC_DIV16	0x00000001
#define	BRGC_EXTC_BCLK	0x00000000
#define	BRGC_EXTC_CLK2	0x00004000
#define	BRGC_EXTC_CLK6	0x00008000

#define GSMRH_RSYN	0x00000001
#define	GSMRH_RTSM	0x00000002
#define GSMRH_SYNL_EXT	 0x00000000
#define GSMRH_SYNL_4BIT	 0x00000004
#define GSMRH_SYNL_8BIT	 0x00000008
#define GSMRH_SYNL_16BIT 0x0000000C

#define GSMRH_TXSY			0x00000010
#define GSMRH_RFW			0x00000020
#define GSMRH_TFL			0x00000040
#define GSMRH_CTSS			0x00000080
#define GSMRH_CDS			0x00000100
#define GSMRH_CTSP			0x00000200
#define GSMRH_CDP			0x00000400
#define	GSMRH_TTX			0x00000800
#define GSMRH_TRX			0x00001000
#define GSMRH_REVD			0x00002000
#define GSMRH_TCRC_CCITT	0x00000000
#define GSMRH_TCRC_CRC16	0x00004000
#define GSMRH_TCRC_CRC32	0x0000C000
#define GSMRH_GDE			0x00010000

#define	GSMRL_TEND	0x00040000
#define	GSMRL_ENR	0x00000020
#define	GSMRL_ENT	0x00000010

#define GSMRL_NRZI	0x00000900 
#define GSMRL_TCI   0x10000000

#define	HDLC_MODE_NOF_SHIFT	12

#define	CPMCMD_RST		0x8000
#define	CPMCMD_FLG		0x0001
#define	CPMCMD_INIT_TX_RX	0x0000
#define CPMCMD_RESTART_TX   0x0600

#define SCCE_GLR	0x1000
#define SCCE_GLT	0x0800
#define	SCCE_RXF	0x0008
#define	SCCE_TXB	0x0002
#define SCCE_TXE    0x0010
#define	SCCE_ALL	0x3FFF

/* Cable ID bits/masks */
#define	CABLE_ID_UNKNOWN		0xFF	/* Impossible value */
#define	CABLE_ID_MASK			(PC12|PC13|PC14|PC15)
#define	CABLE_ID_V11			0x00
#define CABLE_ID_V11A			0x06
#define	CABLE_ID_V35			0x04	
#define CABLE_ID_V35A			0x0E
#define	CABLE_ID_V24			0x08	
#define CABLE_ID_V36			0x0C
#define CABLE_ID_EIA530			0x02
#define	CABLE_ID_EIA449			0x0A
#define CABLE_ID_CPCI_V11		0x01
#define	CABLE_ID_CPCI_V35		0x05
#define	CABLE_ID_CPCI_V24		0x09
#define	CABLE_ID_CPCI_V36		0x0D
#define	CABLE_ID_CPCI_EIA530	0x03
#define	CABLE_ID_CPCI_EIA449	0x0B
#define CABLE_ID_LOOPBACK_GOOD	0x40
#define CABLE_ID_LOOPBACK_BAD	0x41

#define	CABLE_ID_NONE		(PC12|PC13|PC14|PC15)

/* Driver MUX ID's */
#define	OP0		0x00000040
#define	OP1		0x00000080
#define	OP2		0x00000040
#define	OP3		0x00000080

#endif

