/*++
 * Copyright (c) 1990-96 Digi International Inc., All Rights Reserved
 * 
 * This software contains proprietary and confidential information of Digi
 * International Inc.  By accepting transfer of this copy, Recipient agrees
 * to retain this software in confidence, to prevent disclosure to others,
 * and to make no use of this software other than that for which it was
 * delivered.  This is an unpublished copyrighted work of Digi International
 * Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 * prohibited.
 * 
 * Restricted Rights Legend
 *
 * Use, duplication, or disclosure by the Government is subject to
 * restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 * Technical Data and Computer Software clause at DFARS 252.227-7031 or
 * subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 * Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 * Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 *
 * Last Update: $Date: 10/22/97 11:56a $
 *
 * $Header: /Components/Windows/NT/Sync/Build/Mp570/def64570.h 4     10/22/97 11:56a Darinh $
 *
 * Revision History:
 * $Log: /Components/Windows/NT/Sync/Build/Mp570/def64570.h $
 * 
 * 4     10/22/97 11:56a Darinh
 * Changes to make multiple board installations work better.
 * 
 * 3     6/06/97 1:47p Darinh
 * Everything seems functional, but more testing is required.
 * 
 * 2     4/08/97 4:55p Darinh
 * Changes made to correspond to the new DigiUtil library.  It
 * successfully transmits data!  I don't know about receiving data yet.
 * 
 * 1     4/02/97 10:08a Darinh
 * Initial checkin; ISA cards initialize, but do not pass data.
 * 
--*/

#ifndef _DEF64570_H
#define _DEF64570_H

//
// Definitions for Interrupt Control Register (ICR_)
//
#define ICR_IAK_NONACK			0x00
#define ICR_IAK_SINGLE_ACK		0x20
#define ICR_IAK_DOUBLE_ACKS		0x40

#define ICR_VOS_IMVR			0x10

//
// Definitions for MSCI Mode Register 0 (MD0_)
//
#define MD0_PRTCL_ASYNC			0x00
#define MD0_PRTCL_MONOSYNC		0x20
#define MD0_PRTCL_BISYNC		0x40
#define MD0_PRTCL_EXTSYNC		0x60
#define MD0_PRTCL_HDLC			0x80
#define MD0_PRTCL_LOOP			0xA0

#define MD0_AUTO				0x10
#define MD0_CRC_ENABLE			0x04
#define MD0_CRC16				0x00
#define MD0_CRC_CCITT			0x02
#define MD0_CRC_INIT_0			0x00
#define MD0_CRC_INIT_1			0x01

//
// Definitions for MSCI Mode Register 1 (MD1_)
//
#define MD1_NO_ADDR_CHECK		0x00
#define MD1_SINGLE_ADDR1		0x40
#define MD1_SINGLE_ADDR2		0x80
#define MD1_DUAL_ADDRS			0xC0

//
// Definitions for MSCI Mode Register 2 (MD2_)
//
#define MD2_NRZ					0x00
#define MD2_NRZI				0x20

#define MD2_ADPLL8				0x00
#define MD2_ADPLL16				0x08
#define MD2_ADPLL32				0x10

#define MD2_FULL_DUPLEX			0x00
#define MD2_AUTO_ECHO			0x01
#define MD2_LOOP_BACK			0x03

//
// Definitions for MSCI Control Register (CTL_)
//
#define MSCI_CTL_RTS_HIGH		0x01
#define MSCI_CTL_IDLC_PATTERN	0x10
#define MSCI_CTL_UDRNC_ENABLE	0x20

//
// Definitions for MSCI Command Register (CMD_)
//
#define CMD_TX_RESET			0x01
#define CMD_TX_ENABLE			0x02
#define CMD_TX_DISABLE			0x03
#define CMD_TX_CRC_INIT			0x04
#define CMD_TX_CRC_EXCLUSION	0x05
#define CMD_TX_EOM				0x06
#define CMD_TX_ABORT			0x07
#define CMD_TX_MP				0x08
#define CMD_TX_BUFF_CLEAR		0x09

#define CMD_RX_RESET			0x11
#define CMD_RX_ENABLE			0x12
#define CMD_RX_DISABLE			0x13
#define CMD_RX_CRC_INIT			0x14
#define CMD_RX_MSG_REJECT		0x15
#define CMD_RX_FIND_MP			0x16
#define CMD_RX_CRC_EXCLUSION	0x17
#define CMD_RX_FORCE_CRC		0x18

#define CMD_CHANNEL_RESET		0x21
#define CMD_ENTER_HUNT_MODE		0x31

//
// Definitions for Interrupt Sources for SCA0 (IS0_)
// Bit 7 and 6 of IMVR are set to 0
//
#define IS0_MSCI0_RXRDY			0x04
#define IS0_MSCI0_TXRDY			0x06
#define IS0_MSCI0_RXINT			0x08
#define IS0_MSCI0_TXINT			0x0A
#define IS0_MSCI1_RXRDY			0x24
#define IS0_MSCI1_TXRDY			0x26
#define IS0_MSCI1_RXINT			0x28
#define IS0_MSCI1_TXINT			0x2A
#define IS0_DMAC0_DMIA0			0x14
#define IS0_DMAC0_DMIB0			0x16
#define IS0_DMAC1_DMIA1			0x18
#define IS0_DMAC1_DMIB1			0x1A
#define IS0_DMAC2_DMIA2			0x34
#define IS0_DMAC2_DMIB2			0x36
#define IS0_DMAC3_DMIA3			0x38
#define IS0_DMAC3_DMIB3			0x3A
#define IS0_TIMER0				0x1C
#define IS0_TIMER1				0x1E
#define IS0_TIMER2				0x3C
#define IS0_TIMER3				0x3E

//
// Definitions for Interrupt Sources for SCA1 (IS1_)
// Bit 7 and 6 of IMVR are set to 0 and 1
//
#define IS1_MSCI0_RXRDY			0x44
#define IS1_MSCI0_TXRDY			0x46
#define IS1_MSCI0_RXINT			0x48
#define IS1_MSCI0_TXINT			0x4A
#define IS1_MSCI1_RXRDY			0x64
#define IS1_MSCI1_TXRDY			0x66
#define IS1_MSCI1_RXINT			0x68
#define IS1_MSCI1_TXINT			0x6A
#define IS1_DMAC0_DMIA0			0x54
#define IS1_DMAC0_DMIB0			0x56
#define IS1_DMAC1_DMIA1			0x58
#define IS1_DMAC1_DMIB1			0x5A
#define IS1_DMAC2_DMIA2			0x74
#define IS1_DMAC2_DMIB2			0x76
#define IS1_DMAC3_DMIA3			0x78
#define IS1_DMAC3_DMIB3			0x7A
#define IS1_TIMER0				0x5C
#define IS1_TIMER1				0x5E
#define IS1_TIMER2				0x7C
#define IS1_TIMER3				0x7E

//
// Definitions for Interrupt Enable and Interrupt Status bit mask
//
#define INT_DMIA0_ENABLE		0x01
#define INT_DMIB0_ENABLE		0x02
#define INT_DMIAB0_ENABLE		0x03
#define INT_DMIA1_ENABLE		0x04
#define INT_DMIB1_ENABLE		0x08
#define INT_DMIAB1_ENABLE		0x0C
#define INT_DMIAB01_ENABLE		0x0F
#define INT_DMIA2_ENABLE		0x10
#define INT_DMIB2_ENABLE		0x20
#define INT_DMIAB2_ENABLE		0x30
#define INT_DMIA3_ENABLE		0x40
#define INT_DMIB3_ENABLE		0x80
#define INT_DMIAB3_ENABLE		0xC0
#define INT_DMIAB23_ENABLE		0xF0

#define INT_RXINT0_ENABLE		0x04
#define INT_RXINT1_ENABLE		0x40
#define INT_TXINT0_ENABLE		0x08
#define INT_TXINT1_ENABLE		0x80

#define INT_T3IRQ_ENABLE		0x80
#define INT_T2IRQ_ENABLE		0x40
#define INT_T1IRQ_ENABLE		0x20
#define INT_T0IRQ_ENABLE		0x10

#define INT_MSCI_CHANNEL0		0x0F0C
#define INT_MSCI_CHANNEL1		0xF0C0

//
// Definitions for DMA Status Register (DMAC_DSR_)
//
#define DMAC_DSR_EOTM			0x80
#define DMAC_DSR_EOMM			0x40
#define DMAC_DSR_BOFM			0x20
#define DMAC_DSR_COFM			0x10
#define DMAC_DSR_DEE			0x02
#define DMAC_DSR_DWED			0x01

#define DMAC_DSR_CLEAR_EOT		0x81
#define DMAC_DSR_CLEAR_EOM		0x41
#define DMAC_DSR_CLEAR_BOF		0x21
#define DMAC_DSR_CLEAR_COF		0x11

#define DMAC_DCR_DMA_SW_ABORT	0x01
#define DMAC_DCR_CLEAR_FCT		0x02

#define DMAC_PRIORITY			0x40

#define DMAC_DMER_ENABLE		0x80

//
// Definitions for DMA Mode Register (DMAC_DMR_)
//
#define DMAC_DMR_TMOD_CBT		0x10
#define DMAC_DMR_NF_MF			0x04
#define DMAC_DMR_CNTE_CBT_FCTE	0x02


// Definitions for DMA Priority Control Register (DMAC_PCR_)
#define DMAC_PCR_BRC_ONE_DMA		0x10
#define DMAC_PCR_CCC					0x08
#define DMAC_PCR_CCC_ROUND_ROBIN	0x04


//
// Definitions for MSCI Interrupt Enable Register 0
//
#define MSCI_IE0_RXRDYE			0x01
#define MSCI_IE0_TXRDYE			0x02
#define MSCI_IE0_RXINTE			0x40
#define MSCI_IE0_TXINTE			0x80

//
// Definitions for MSCI Interrupt Enable Register 1
//
#define MSCI_IE1_IDLDE			0x01
#define MSCI_IE1_ABTDE			0x02
#define MSCI_IE1_CDCDE			0x04
#define MSCI_IE1_CCTSE			0x08
#define MSCI_IE1_FLGDE			0x10
#define MSCI_IE1_IDLE			0x40
#define MSCI_IE1_UDRNE			0x80

//
// Definitions for MSCI Interrupt Enable Register 2
//
#define MSCI_IE2_CRCEE			0x04
#define MSCI_IE2_OVRNE			0x08
#define MSCI_IE2_RBITE			0x10
#define MSCI_IE2_ABTE			0x20
#define MSCI_IE2_SHRTE			0x40
#define MSCI_IE2_EOME			0x80

//
// Definitions for MSCI Status Register 1 Mask
//
#define MSCI_ST1_CDCDM			0x04
#define MSCI_ST1_CCTSM			0x08
#define MSCI_ST1_IDLM			0x40
#define MSCI_ST1_UDRNM			0x80

//
// Definitions for MSCI Status Register 3 Mask
//
#define MSCI_ST3_RXENBLM		0x01
#define MSCI_ST3_TXENBLM		0x02
#define MSCI_ST3_DCDM			0x04
#define MSCI_ST3_CTSM			0x08
#define MSCI_ST3_SLOOPM			0x20

//
// Definitions for DMAC DCR
//
#define DCR_SOFTWARE_ABORT		0x01
#define DCR_FCT_CLEAR			0x02

//
// Definitions for TIMER Control/Status Register (TCSR_)
//
#define TCSR_TMEE				0x10
#define TCSR_ECMIE				0x40
#define TCSR_CMFM				0x80

//
// Definitions for TIMER Expand Prescale Register (TEPR_)
//
#define TEPR_ECKS0				0x00
#define TEPR_ECKS2				0x01
#define TEPR_ECKS4				0x02
#define TEPR_ECKS8				0x03
#define TEPR_ECKS16				0x04
#define TEPR_ECKS32				0x05
#define TEPR_ECKS64				0x06
#define TEPR_ECKS128			0x07

//
// Definitions for _SCA_MSCI structure
//
typedef struct _SCA_MSCI
{
	//      20, 40
	USHORT	Trb;			// MSCI Tx/Rx Buffer
	UCHAR	St0;			// MSCI Status 0
	UCHAR	St1;			// MSCI Status 1
	UCHAR	St2;			// MSCI Status 2
	UCHAR	St3;			// MSCI Status 3
	UCHAR	Fst;			// MSCI Frame Status
	UCHAR	Rsv_27;				
	//      28, 48
	UCHAR	Ie0;			// MSCI Interrupt Enable 0
	UCHAR	Ie1;			// MSCI Interrupt Enable 1
	UCHAR	Ie2;			// MSCI Interrupt Enable 2
	UCHAR	Fie;			// MSCI Frame Interrupt
	UCHAR	Cmd;			// MSCI Command
	UCHAR	Rsv_2d;				
	UCHAR	Md0;			// MSCI Mode 0
	UCHAR	Md1;			// MSCI Mode 1
	//      30, 50
	UCHAR	Md2;			// MSCI Mode 2
	UCHAR	Ctl;			// MSCI Control
	UCHAR	Sa0;			// MSCI Sync Address 0
	UCHAR	Sa1;			// MSCI Sync Address 1
	UCHAR	Idl;			// MSCI Idle Pattern Register
	UCHAR	Tmc;			// MSCI Time Constant 0
	UCHAR	Rxs;			// MSCI Rx Clock Source
	UCHAR	Txs;			// MSCI Tx Clock Source
	//      38, 58
	UCHAR	Trc0;			// MSCI Tx Ready Control 0
	UCHAR	Trc1;			// MSCI Tx Ready Control 1
	UCHAR	Rrc;			// MSCI Rx Ready Control
	UCHAR	Rsv_3b;				
	USHORT	Cst01;			// MSCI Current Status 01
	UCHAR	Rsv_3e;				
	UCHAR	Rsv_3f;				

} SCA_MSCI, *PSCA_MSCI;

//
// Definitions for _SCA_TIMER structure
//
typedef struct _SCA_TIMER
{
	//      60, 68, 70, 78
	USHORT	Tcnt;			// Timer Count
	USHORT	Tcon;			// Timer Constant
	UCHAR	Tcsr;			// Timer Control/Status
	UCHAR	Tepr;			// Timer Expand Prescale
	UCHAR	Rsv_66;
	UCHAR	Rsv_67;

} SCA_TIMER, *PSCA_TIMER;

//
// Definitions for _SCA_DMAC structure
//
typedef struct _SCA_DMAC
{
	//      80, A0, C0, E0
	UCHAR	Barl;			// Chained mode Dest. Addr L
	UCHAR	Barh;			// Chained mode Dest. Addr H
	UCHAR	Barb;			// Chained mode Dest. Addr B
	UCHAR	Rsv_83;
	UCHAR	Rsv_84;
	UCHAR	Rsv_85;
	UCHAR	Cpb;			// Chain Pointer Base
	UCHAR	Rsv_87;
	//      88, A8, C8, E8
	USHORT	Cda;			// DMA Current Descriptor
	USHORT	Eda;			// DMA Error Descriptor
	USHORT	Rbl;			// DMA Receive Buffer Length
	USHORT	Bcr;			// DMA Byte Count Register
	//      90, B0, D0, F0
	UCHAR	Dsr;			// DMA Status Register
	UCHAR	Dmr;			// DMA Mode Register
	UCHAR	Rsv_92;
	UCHAR	Fct;			// DMA Frame End Interrupt Count
	UCHAR	Dir;			// DMA Interrupt Enable
	UCHAR	Dcr;			// DMA Command Register
	UCHAR	Rsv_96;
	UCHAR	Rsv_97;
	//      98, B8, D8, F8
	UCHAR	Rsv_98;
	UCHAR	Rsv_99;
	UCHAR	Rsv_9a;
	UCHAR	Rsv_9b;
	UCHAR	Rsv_9c;
	UCHAR	Rsv_9d;
	UCHAR	Rsv_9e;
	UCHAR	Rsv_9f;

} SCA_DMAC, *PSCA_DMAC;

//
// Structure definitions for SCA Registers
//
typedef struct _SCA_REG
{
	// 00
	UCHAR	ComLpr;			// Low Power Register
	UCHAR	Rsv_01;
	UCHAR	ComPabr0;		// Physical Address Boundary 0
	UCHAR	ComPabr1;		// Physical Address Boundary 1
	UCHAR	ComWcrl;		// Wait Control Low
	UCHAR	ComWcrm;		// Wait Control Medium
	UCHAR	ComWcrh;		// Wait Control High
	UCHAR	Rsv_07;
	// 08
	UCHAR	ComPcr;			// Priority Control
	UCHAR	ComDmer;		// DMA Master Enable
	UCHAR	Rsv_0a;
	UCHAR	Rsv_0b;
	UCHAR	Rsv_0c;
	UCHAR	Rsv_0d;
	UCHAR	Rsv_0e;
	UCHAR	Rsv_0f;
	// 10
	USHORT	ComIsr01;		// Interrupt Status 0 and 1
	UCHAR	ComIsr2;		// Interrupt Status 2
	UCHAR	Rsv_13;
	UCHAR	ComIer0;		// Interrupt Enable 0
	UCHAR	ComIer1;		// Interrupt Enable 1
	UCHAR	ComIer2;		// Interrupt Enable 2
	UCHAR	Rsv_17;
	// 18
	UCHAR	ComItcr;		// Interrupt Control
	UCHAR	Rsv_19;
	UCHAR	ComIvr;			// Interrupt Vector
	UCHAR	Rsv_1b;
	UCHAR	ComImvr;		// Interrupt Modified Vector
	UCHAR	Rsv_1d;
	UCHAR	Rsv_1e;
	UCHAR	RSv_1f;
	
	SCA_MSCI	MsciRegs[2];		// MSCI Registers
	SCA_TIMER	TimerRegs[4];		// Timers
	SCA_DMAC	DmacRegs[4];		// DMA channels

} SCA_REGS, *PSCA_REGS;

//
// Definitions for SDLC frame
//

//
// Structure definitions for SDLC frame
//
typedef struct _SDLC_BUFFER
{
	UCHAR	SdlcAddr;						// SDLC address field

#define POLLBIT_ON              0x10
	UCHAR	SdlcCtrl;						// SDLC Control field

#define DEFAULT_DATA_SIZE        254
	UCHAR	Data[DEFAULT_DATA_SIZE];		// TH + RH + RU

} SDLC_BUFFER, *PSDLC_BUFFER;

#define	SDLC_FRAME_SIZE		sizeof (SDLC_BUFFER)
#define	DEFAULT_FRAME_SIZE	SDLC_FRAME_SIZE
//
// Definitions for FrameStatus (FS_)
// This is used in FrameStatus in the descriptor.
//
#define FS_ERROR_FRAME			0x01
#define FS_CONTINUE_FRAME		0x02
#define FS_GOOD_FRAME			0x04
#define FS_END_FRAME			0x08

#define DMA_RX_DSP_CHAINS		0x01
#define DMA_TX_DSP_CHAINS		0x02

//
// Definitions for DMA Chain Descriptor DMAC Status (DMAC_STATUS_)
// This is used for DmaStatus in the descriptor
//
// This is used for Receive DMIB interrupt
#define DMAC_STATUS_SHRTM		0x40
#define DMAC_STATUS_ABORTM		0x20
#define DMAC_STATUS_RBITM		0x10
#define DMAC_STATUS_OVRRNM		0x08
#define DMAC_STATUS_CRCM		0x04

#define DMAC_STATUS_MASK		0xFC

//This is use for transmit DMIB interrupt
#define DMAC_STATUS_EOM			0x80
#define DMAC_STATUS_EOT			0x01
#define DMAC_STATUS_EOTEOM		0x81

//
// Structure definitions for DMA Chain Descriptor
//
typedef struct _DMA_CHAIN
{
	USHORT	NextChain;			// Next descriptor
	USHORT	BufferAddress;		// Buffer address (first 16 bits)
	UCHAR	BuffAddrExt;		// Buffer address extension
	USHORT	DataLen;			// Length of the data in the buffer
	UCHAR	DmaStatus;			// DMA Status
	UCHAR	FrameStatus;		// Used by device driver

	UCHAR	Padding2[6];		// Needs to be 4-byte aligned for PCI

} DMA_CHAIN, *PDMA_CHAIN;

#define	DMA_CHAIN_SIZE		sizeof(DMA_CHAIN)

#endif // _DEF64570_H

