#ident "$Id: sca.h,v 1.3 1996/05/20 20:29:33 gary Exp $"
/*****************************************************************************
 * Copyright (c) 1988-95 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1995
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/


/******************************************************************
 *
 *  SpiderX25 - Embedded Code
 *
 *  Copyright 1992  Spider Systems Limited
 *
 *  SCA.H
 *
 *    Device specific driver (C part)
 *
 ******************************************************************/


/*
 *      sca.h
 *       /projects/common/PBRAIN/SCCS/pbrainE/dev/embed/wan/77/s.cd2400.h
 *      @(#)cd2400.h	1.2
 *
 *      Last delta created      19:53:35 5/7/92
 *      This file extracted     13:03:27 10/13/92
 *
 *      Modifications:
 *
 */

#define TXEXSTATUS	0x8090L
#define TXINTSTATUS	0x0020L
#define TXERRORSTATUS	0x0800L
#define RXSXSTATUS	0x009E0000L
#define RXEXSTATUS	0x00200000L
#define	RXERRORSTATUS	0x00010000L

#define HDLCTXEOM	0x0080L
#define HDLCTXEOT	0x0010L
#define HDLCURUN	0x8000L
#define HDLCRXEOM	0x800000L
#define HDLCRXEOT	0x100000L
#define HDLCRXORUN	0x080000L
#define HDLCRXABORT	0x200000L
#define	HDLCRXCRC	0x040000L
#define	HDLCRXOFLOW	0x020000L

struct siotab_ent {
                  caddr_t reg;          /* pointer to reg to initialise */
                  uint8   size;         /* size of reg 0=8,1=16 */
                  uint16  value;        /* value to write to register */
                  uint8   clkopt;       /* is an option when clocking */
                  uint16  cvalue;        /* value to write to register */
};

#define HS_DEV	VMO(HS, 0xa2000000)

#define	NSCA	2	/* number of sca full duplex channels */
#define	NSCATIMER	4	/* number of timers on SCA */
#define	NSCADMA	4	/* number of dma channels */

#if 0
#define	SCA_BUFF_SIZE	1024	/* size of division of local dram for 1 SCA buffer */
#else
#define	SCA_BUFF_SIZE	0x380	/* size of division of local dram for 1 SCA buffer */
#endif

struct sca
{
    uint8	sca_lpr;		/* Low Power Register */
    uint16	sca_pad1;
    uint8	sca_pabr0;		/* Physical Address Boundary 0 */
    uint8	sca_pabr1;		/* Physical Address Boundary 1 */
    uint16	sca_pad2;
    uint8	sca_wcrl;		/* Wait Control Low */
    uint8	sca_wcrm;		/* Wait Control Medium */
    uint16	sca_pad3;
    uint8	sca_wcrh;		/* Wait Control High */
    uint16	sca_pad4;
    uint8	sca_pcr;		/* Priority Control */
    uint8	sca_dmer;		/* DMA Master Enable */
    uint32	sca_pad5[3];

    uint16	sca_isr01;		/* Interrupt Status 01 */
    uint16	sca_pad6;
    uint8	sca_isr2;		/* Interrupt Status 2 */
    uint16	sca_pad7;
    uint8	sca_ie0;		/* Interrupt Enable 0 */
    uint8	sca_ie1;		/* Interrupt Enable 1 */
    uint16	sca_pad8;
    uint8	sca_ie2;		/* Interrupt Enable 2 */
    uint16	sca_pad9;
    uint8	sca_itcr;		/* Interrupt Control */
    uint16	sca_pad10;
    uint8	sca_ivr;		/* Interrupt Vector */
    uint16	sca_pad11;
    uint8	sca_imvr;		/* Interrupt Modified Vector */
    uint32	sca_pad12;

    struct chan
    {
	uint16	chan_trb;		/* MSCI Tx/Rx Buffer */
	uint16	chan_pad1;
	uint16	chan_st01;		/* MSCI Status 01 */
	uint16	chan_pad2;
	uint16	chan_st23;		/* MSCI Status 23 */
	uint16	chan_pad3;
	uint16	chan_fst;		/* MSCI Frame Status */
	uint16	chan_pad4;
	uint8	chan_ie0;		/* MSCI Interrupt Enable 0 */
	uint8	chan_ie1;		/* MSCI Interrupt Enable 1 */
	uint16	chan_pad5;
	uint8	chan_ie2;		/* MSCI Interrupt Enable 2 */
	uint8	chan_fie;		/* MSCI Frame Interrupt */
	uint16	chan_pad6;
	uint8	chan_cmd;		/* MSCI Command */
	uint16	chan_pad7;
	uint8	chan_md0;		/* MSCI Mode 0 */
	uint8	chan_md1;		/* MSCI Mode 1 */
	uint16	chan_pad8;

	uint8	chan_md2;		/* MSCI Mode 2 */
	uint8	chan_ctl;		/* MSCI Control */
	uint16	chan_pad9;
	uint8	chan_sa0;		/* MSCI Sync Address 0 */
	uint8	chan_sa1;		/* MSCI Sync Address 1 */
	uint16	chan_pad10;
	uint8	chan_idl;		/* MSCI Idle Pattern Register */
	uint8	chan_tmc;		/* MSCI Time Constant 0 */
	uint16	chan_pad11;
	uint8	chan_rxs;		/* MSCI Rx Clock Source */
	uint8	chan_txs;		/* MSCI Tx Clock Source */
	uint16	chan_pad12;
	uint8	chan_trc0;		/* MSCI Tx Ready Control 0 */
	uint8	chan_trc1;		/* MSCI Tx Ready Control 1 */
	uint16	chan_pad13;
	uint8	chan_rrc;		/* MSCI Rx Ready Control */
	uint16	chan_pad14;
	uint16	chan_cst01;		/* MSCI Current Status 01 */
	uint32	chan_pad15;
    }
	sca_chan[NSCA];			/* MSCI Registers */

    struct sca_timer
    {
	uint16	timer_tcnt;		/* Timer Count */
	uint16	timer_pad1;
	uint16	timer_tcon;		/* Timer Constant */
	uint16	timer_pad2;
	uint8	timer_tcsr;		/* Timer Control/Status */
	uint16  timer_tepr;		/* Timer Expand Prescale */
	uint32	timer_pad3;
    }
	sca_timer[NSCATIMER];			/* Timers */

    struct sca_dma
    {
	uint16	dma_pad1[6];
	uint8	dma_cpb;		/* Chain Pointer Base */
	uint16	dma_pad2;
	uint16	dma_cda;		/* DMA Current Descriptor */
	uint16	dma_pad3;
	uint16	dma_eda;		/* DMA Error Descriptor */
	uint16	dma_pad4;
	uint16	dma_rbl;		/* DMA Receive Buffer Length */
	uint16	dma_pad5;
	uint16	dma_bcr;		/* DMA Byte Count Register */
	uint16	dma_pad6;

	uint8	dma_dsr;		/* DMA Status Register */
	uint8	dma_dmr;		/* DMA Mode Register */
	uint8	dma_pad7[3];
	uint8	dma_fct;		/* DMA Frame End Interrupt Count */
	uint16	dma_pad8;
	uint8	dma_dir;		/* DMA Interrupt Enable */
	uint8	dma_dcr;		/* DMA Command Register */
	uint32	dma_pad9[5];
    } sca_dma[NSCADMA];			/* DMA channels */
};

struct dma_desc {
        uint16 dpad;			/* padding to force contiguousness */
        uint16 chptr;			/* chain pointer */
        uint32 bptr;			/* buffer ptr    */
        uint16 blen;			/* buffer len    */
        uint8 status;			/* buffer status */
	uint8 padding;			/* force 32-bit alignment */
	mblk_t * this_mp;		/* Descriptor's objective */
};

struct desctab {
	struct dma_desc desc[NSCA][16];
};

struct basetab {
	uint8 * base[NSCA][16];
};

