/*++
 * Copyright (c) 1990-96 Digi International Inc., All Rights Reserved
 * 
 * This software contains proprietary and confidential information of Digi
 * International Inc.  By accepting transfer of this copy, Recipient agrees
 * to retain this software in confidence, to prevent disclosure to others,
 * and to make no use of this software other than that for which it was
 * delivered.  This is an unpublished copyrighted work of Digi International
 * Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 * prohibited.
 * 
 * Restricted Rights Legend
 *
 * Use, duplication, or disclosure by the Government is subject to
 * restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 * Technical Data and Computer Software clause at DFARS 252.227-7031 or
 * subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 * Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 * Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 *
 * Last Update: $Date: 10/22/97 11:56a $
 *
 * $Header: /Components/Windows/NT/Sync/Build/Mp570/def570.h 3     10/22/97 11:56a Darinh $
 *
 * Revision History:
 * $Log: /Components/Windows/NT/Sync/Build/Mp570/def570.h $
 * 
 * 3     10/22/97 11:56a Darinh
 * Changes to make multiple board installations work better.
 * 
 * 2     6/06/97 1:47p Darinh
 * Everything seems functional, but more testing is required.
 * 
 * 1     4/02/97 10:08a Darinh
 * Initial checkin; ISA cards initialize, but do not pass data.
 * 
--*/

#ifndef _DEF570_H
#define _DEF570_H

//
//  DIGI SYNC/570 or SYNC/570i Board Interfaces for ISA/MCA
//  Definitions for accessing the registers (BaseIOAddress + x)
//
#define REG570_BUS_MEM_INTERF	0x03
#define REG570_ADAPTER_REV		0x04
#define REG570_PORT_NUMBER		0x05
#define REG570_HANDSHAKE		0x06
#define REG570_DCD_INT_STATUS	0x07
#define REG570_MEM_SCA			0x08
#define REG570_TXCLK_DTR01		0x09
#define REG570_SEC_PAL			0x0A
#define REG570_INT_ACK01		0x0B
#define REG570_INT_SEL			0x0C
#define REG570_MEM_SEL			0x0D
#define REG570_INT_ACK23		0x0E
#define REG570_TXCLK_DTR23		0x0E

//
//  DIGI SYNC/570 or SYNC/570i Board Interfaces for PCI
//  Definitions for accessing the registers (BaseIOAddress + x)
//
#define REG570PCI_BUS_MEM_INTERF	0x0C
#define REG570PCI_ADAPTER_REV		0x10
#define REG570PCI_PORT_NUMBER		0x14
#define REG570PCI_HANDSHAKE			0x18
#define REG570PCI_DCD_INT_STATUS	0x1C
#define REG570PCI_TXCLK_DTR01		0x24
#define REG570PCI_SEC_PAL			0x28
#define REG570PCI_INT_ACK01			0x2C
#define REG570PCI_INT_ACK23			0x38
#define REG570PCI_TXCLK_DTR23		0x38
#define	REG570PCI_DCDD_INT_CTRL		0x3C
#define	REG570PCI_PIM_CTRL			0x4C
#define REG570PCI_INT_SCOREBOARD	0x50

//
// Bus, Memory and Interface Type register (BMI_)
// REG570_BUS_MEM_INTERF	0x03
//
#define BMI_COM_232				0x00
#define BMI_COM_V35_232			0x20
#define BMI_COM_530				0x40
#define BMI_COM_X21				0x60
#define BMI_COM_SW56K			0x80
#define BMI_COM_530_X21			0xC0
#define BMI_COM_MASK			0xE0

//
// Adapter Revision register (AR_)
// REG570_ADAPTER_REV	0x04
//
#define AR_MASK					0x07

//
// Port Number register (PN_)
// REG570_PORT_NUMBER 0x05
//
#define PN_2PORTS				0x02
#define PN_4PORTS				0x04

//
// Supported Handshake register (SH_)
// REG570_HANDSHAKE 0x06
//
#define SH_DTR					0x01
#define SH_RTS					0x02
#define SH_CTS					0x10
#define SH_DSR					0x20
#define SH_RI					0x40
#define SH_DCD					0x80

//
// DCD and Interrupt Status (DIS_)
// REG570_DCD_INT_STATUS 0x07
//
#define DIS_BOARD_INTE			0x01
#define DIS_DCD0E				0x02
#define DIS_DCD1E				0x04
#define DIS_DCD2E				0x08
#define DIS_DCD3E				0x10
#define DIS_INT0P				0x20
#define DIS_INT1P				0x40

//
// Memory and Serial Communication Adapter (SCA) Enable register (MSCA_)
// REG570_MEM_SCA 0x08
//
#define MSCA_WIN0				0x01
#define MSCA_WIN1				0x02
#define MSCA_WIN2				0x04
#define MSCA_WIN3				0x08
#define MSCA_WIN4				0x10
#define MSCA_SEL_SCA			0x20
#define MSCA_EN_SCA				0x40
#define MSCA_MEM				0x80

#define MSCA_WIN_MASK			0x1F

#define MSCA_MEM_SCA0			0xC0
#define MSCA_MEM_SCA1			0xE0

//
// Transmit Clock and DTR Control 0 and 1 register (TCD01_)
// REG570_TXCLKDTR01 0x09
//
#define TCD01_TX0E				0x01
#define TCD01_TX1E				0x02
#define TCD01_DTR0				0x04
#define TCD01_DTR1				0x08
#define TCD01_TXCS0I			0x10
#define TCD01_TXCS1I			0x20
#define TCD01_RES				0x40

#define TCD01_DTRTX0_ENABLE		0x05
#define TCD01_DTRTX0_ENABLE_56	0x15
#define TCD01_DTRTX1_ENABLE		0x0A

//
// Interrupt Select register (IS_)
// REG570_INT_SEL 0x0C
//
#define IS_CEN					0x01
#define IS_ISEL0				0x02
#define IS_ISEL1				0x04
#define IS_ISEL2				0x08
#define IS_CMA14				0x10
#define IS_CMA15				0x20

#define IS_IRQ_DISABLE			0x00
#define IS_IRQ3					0x02
#define IS_IRQ5					0x04
#define IS_IRQ7					0x06
#define IS_IRQ10				0x08
#define IS_IRQ11				0x0A
#define IS_IRQ12				0x0C
#define IS_IRQ15				0x0E

#define IS_D0000                0x00
#define IS_D4000                0x10
#define IS_D8000                0x20
#define IS_DC000                0x30

//
// Memory Select register (MS_)
// REG570_MEM_SEL 0x0D
//
#define MS_CMA16				0x01
#define MS_CMA17				0x02
#define MS_CMA18				0x04
#define MS_CMA19				0x08
#define MS_CMA20				0x10
#define MS_CMA21				0x20
#define MS_CMA22				0x40
#define MS_CMA23				0x80

#define MS_MEM					0x0D

//
// Transmit Clock and DTR Control 2 and 3 register (TCD23_)
// REG570_TXCLKDTR23 0x0E
//
#define TCD23_TX2				0x01
#define TCD23_TX3				0x02
#define TCD23_DTR2				0x04
#define TCD23_DTR3				0x08
#define TCD23_TXCS2I			0x10
#define TCD23_TXCS3I			0x20

#define TCD23_DTRTX2_ENABLE		0x05
#define TCD23_DTRTX3_ENABLE		0x0A

//
// Adapter Flag
//
#define AF_INIT					0x01
#define AF_RESET				0x02
#define AF_ENABLE				0x04
#define AF_CLEAR_MEMORY			0x08

//
// RTS Write Flag
//
#define LOWER					((ULONG) 0x01)
#define RAISE					((ULONG) 0x02)

#endif // _DEF570_H
