/*++
 * Copyright (c) 1990-96 Digi International Inc., All Rights Reserved
 * 
 * This software contains proprietary and confidential information of Digi
 * International Inc.  By accepting transfer of this copy, Recipient agrees
 * to retain this software in confidence, to prevent disclosure to others,
 * and to make no use of this software other than that for which it was
 * delivered.  This is an unpublished copyrighted work of Digi International
 * Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
 * prohibited.
 * 
 * Restricted Rights Legend
 *
 * Use, duplication, or disclosure by the Government is subject to
 * restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
 * Technical Data and Computer Software clause at DFARS 252.227-7031 or
 * subparagraphs (c)(1) and (2) of the Commercial Computer Software -
 * Restricted Rights at 48 CFR 52.227-19, as applicable.
 *
 * Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
 *
 *
 * Last Update: $Date: 10/22/97 11:56a $
 *
 * $Header: /Components/Windows/NT/Sync/Build/Mp570/board.h 6     10/22/97 11:56a Darinh $
 *
 * Revision History:
 * $Log: /Components/Windows/NT/Sync/Build/Mp570/board.h $
 * 
 * 6     10/22/97 11:56a Darinh
 * Changes to make multiple board installations work better.
 * 
 * 5     9/08/97 3:44p Darinh
 * A variety of changes, including Data General fixes are included.
 * 
 * 4     7/15/97 1:05p Darinh
 * Added DigiLogError statements and message file, altered code to function
 * in DStreams environment and SNA environment with a conditional
 * compilation.
 * 
 * 3     6/06/97 1:47p Darinh
 * Everything seems functional, but more testing is required.
 * 
 * 2     4/08/97 4:55p Darinh
 * Changes made to correspond to the new DigiUtil library.  It
 * successfully transmits data!  I don't know about receiving data yet.
 * 
 * 1     4/02/97 10:08a Darinh
 * Initial checkin; ISA cards initialize, but do not pass data.
 * 
--*/

#ifndef BOARD_H_
#define	BOARD_H_

#include "def64570.h"
#include "dsmp.h"



extern PDRIVER_OBJECT	pGlobalDriverObject;

//
//  PCI Identification constants used in card identification
//
#define DIGI_PCI_VENDOR_ID						0x112f  // Arnet vendor ID
#define DIGI_PCI_VENDOR_ID_NEW					0x114f  // Digi vendor ID

#define DIGI_PCI_SYNC570I_2PORT_LIN				0x5012  // device id
#define DIGI_PCI_SYNC570I_4PORT_LIN				0x5013  // device id

#define DEV_NAME_LEN	24

typedef struct _CONFIGDATA
{
	UCHAR	DisplayName[24];	// Device Object Display Name (in ASCII)
	UCHAR	DeviceName[DEV_NAME_LEN];		// Device Object Visible Name (in ASCII)
	ULONG	BaseIoAddress;		// Base I/O address (in hex)
	ULONG	WindowAddress;		// Memory Winow address (in hex)
	UCHAR	Irql;				// IRQ Level (in hex)
	CHAR	PortNumber;			// Line/Port Number (in hex, start from 0)
	CHAR	LineSpeed;			// Line Speed
				// 1 = 2400
				// 2 = 4800
				// 3 = 9600
				// 4 = 19200
				// 5 = 38400
				// 6 = 56000
				// 7 = 64000
				// 8 = 2400
				// 9 = 4800
				//10 = 9600
				//11 = 19200
				//12 = 38400
				//13 = 56000
	CHAR	InternalClock;

} CONFIGDATA, *PCONFIGDATA;

#define	CONFIGDATA_SIZE		sizeof (CONFIGDATA)

//
// Device Interface Record - Statistics Counters (SC_)
//
#define SC_CRC_ERROR		0
#define SC_LONGFRAME		1
#define SC_SHORTFRAME		2
#define SC_SPARE			3
#define SC_RXABORT			4
#define SC_TXUNDERRUN		5
#define SC_RXOVERRUN		6
#define SC_DCDDROP			7
#define SC_CTSDROP			8
#define SC_DSRDROP			9
#define SC_HARDWAREERROR	10

#define	MAX_SC				11

//
// Device Interface Record
//
typedef struct _INTERFACE_RECORD
{
	int		ReceivedFrames;
	int		TransmitBufferSpace;
	int		StatusEvents;
	UCHAR	InputV24Status;
	UCHAR	OutputV24Status;
	int		StatisticsCounters[MAX_SC];

} IR, *PIR;


struct _DEVICE_EXT;


//
// Digi Board Level Device Object Extension
// This should handle the interrupt from the Digi board regardless of which
// port that cause the interrupt. After the ISR determines the source of the
// interrupt, the CurPortInd should be setup to index to the correct PORTINFO
// and process the interrupt accordingly.
//

#if NT5_BUILD
 
typedef struct _CONTROLLER_EXTENSION
{

	UNICODE_STRING		Name;					//Board name
	WCHAR				NameBuffer[64];			//Board name (for debugging)
	LONG				AdapterLines;			//Number of ports on the card

	//
	// I/O Port information
	//
	PHYSICAL_ADDRESS	PhysIOPort;
	PUCHAR				VirtualIO;				//Mapped Base I/O address
	BOOLEAN				UnMapVirtualIO;			//Should we unmap the I/O ports
	UCHAR				IOSpan;

	//
	// Memory Window information
	//
	PHYSICAL_ADDRESS	PhysWindowAddress;
	PUCHAR				VirtualWindow;			//Mapped memory window
	BOOLEAN				UnMapVirtualWindow;		//Should we unmap the memory
	LONG				WindowSize;				//Mapped Window size
	KSPIN_LOCK			MemoryLock;				//Memory Window spinlock

	//
	// PLX chip information (PCI cards only)
	//
	PHYSICAL_ADDRESS	PhysPlxRegisters;
	PUCHAR				VirtualPlxRegisters;
	BOOLEAN				UnMapVirtualPlxRegisters;
	UCHAR				PlxRegistersSpan;

	//
	// SCA information
	//
	PHYSICAL_ADDRESS	ScaAddress;
	PUCHAR				VirtualSca;
	BOOLEAN				UnMapVirtualSca;

	//
	// Interrupt Line information
	//
	PHYSICAL_ADDRESS	PhysInterruptNumber;
	ULONG				InterruptVector;
	PKINTERRUPT			InterruptObject;
	KIRQL				InterruptLevel;
	KAFFINITY			ProcessorAffinity;
	KINTERRUPT_MODE		InterruptMode;
	BOOLEAN				InterruptShareable;		// Can we share the interrupt?

	//
	// PCI UIB information
	//
	ULONG				ConfigStream;
	ULONG				InterfaceID;

	//
	// An array of DeviceObject pointers
	//
	PDEVICE_OBJECT			pDeviceObject[4];
	struct _DEVICE_EXT *	pDeviceExt[4];

	//
	// Function pointers for IO for this controller.
	//
	UCHAR		(*pIO_IN) ();
	VOID		(*pIO_OUT) ();

	CHAR	NumberOfWindows;

	UCHAR	iBusMemoryCommType;		// card BUS, Memory, and communication type
	UCHAR	iSupportedHandshake;	// Supported handshake on the card
	UCHAR	oMemoryScaEnable;		// Memory and SCA chip enable
	UCHAR	oTxClkDtr01;			// TX Clock and DTR enable for port 0 and 1
	UCHAR	ioInterruptSelect;		// IRQ Level selected on the card
	UCHAR	ioMemorySelect;			// Memory window address selected on card
	UCHAR	oTxClkDtr23;			// TX Clock and DTR enable for port 2 and 3


	//
	// Misc Resource information
	//
	ULONG			BusNumber;
	INTERFACE_TYPE	BusType;

	BOOLEAN			InternalClocking[4];

	PUCHAR			pDigiDcdIntReg;		// DCD and Interrupt status register
	PUCHAR			pDigiMemScaReg;		// Memory and SCA chip enable register

	BOOLEAN			DPCRunning;			// Track if we are in the DPC

	UCHAR			SNALineSpeed[8];	// Temp line speed for SNA config
	UCHAR			DeviceName[8][DEV_NAME_LEN];	//  SNA Device Names

	LIST_ENTRY      ListElement;        // Queue the Controller to the global 
	                                    // controller list

} CONTROLLER_EXT, *PCONTROLLER_EXT;

//
// Port related information data structure
// This data structure is used to stored the information related to a
// particular port on the board. The Board level device object will used to
// handle the interrupt in the ISR, and the Port level device object will be
// used to access the port.
//
typedef struct _DEVICE_EXT
{
	WCHAR			NameBuffer[64];			// Line name
	UNICODE_STRING	Name;					// Line name
	LONG			DeviceOpens;			// Reference count for dev opens

	CHAR			PortNumber;			// Port number
#define FIRST_PORT              0
#define SECOND_PORT             1
#define THIRD_PORT              2
#define FOURTH_PORT             3

	CHAR			LineSpeed;			// Line speed
#define LS_2400BPS              2400
#define LS_4800BPS              4800
#define LS_9600BPS              9600
#define LS_19200BPS             19200
#define LS_38400BPS             38400
#define LS_56000BPS             56000
#define LS_64000BPS             64000
#define LS_128000BPS            128000
#define LS_256000BPS            256000
#define LS_512000BPS            512000
#define LS_1024000BPS           1024000
#define LS_1536000BPS           1536000
#define LS_2048000BPS           2048000

	BOOLEAN		InternalClocking;	// Internal Clocks if true
	UCHAR		LinkOptions;		// Link protocol parameters
	UCHAR		bSdlcCtrl;			// SDLC control field
	USHORT		FifoWatchdog;		// Drop RTS 
	IR			IR;					// Local Interface Record
	DSMP_CONFIG	Config;				// Config record (max frame, baud rate, etc)

	PSCA_REGS	pSca;				// Ptr to SCA registers
	PSCA_MSCI	pScaMsci;			// Ptr to the beginning of MSCI registers
	PSCA_TIMER	pScaTimer;			// Ptr to the beginning of Timer registers
	PSCA_DMAC	pScaRxDmac;			// Ptr to the beginning of Rx DMAC registers
	PSCA_DMAC	pScaTxDmac;			// Ptr to the beginning of Tx DMAC registers

	// DIGI card registers
	UCHAR	DigiMemScaE;			// Memory and SCA chip enable
	UCHAR	DigiDtrTxE;				// DTR and Transmit enable
	UCHAR	DigiTxClkInput;			// Transmit Clock input value
	UCHAR	DigiRegTxClkDtrCtrl;	// TX Clock and DTR control value
	UCHAR	DigiDcdMask;			// DCD signal mask
	UCHAR	DigiIntPendMask;		// SCA Interrupt Pending mask
	PUCHAR	DigiTxClkDtrCtrl;		// TX Clock and DTR Control register
	PUCHAR	DigiIntAckReg;			// SCA Interrupt Acknowledge register

	// Hitachi HD64570 Serial Communication Adapter (SCA)
	UCHAR	ScaMd0;					// MSCI Mode Register 0 value
	UCHAR	ScaMd1;					// MSCI Mode Register 1 value
	UCHAR	ScaMd2;					// MSCI Mode Register 2 value
	UCHAR	ScaCtl;					// MSCI Control Register value
	UCHAR	ScaTmc;					// MSCI Time constant register...
	UCHAR	ScaRxs;					// MSCI Receive Clock Source register value
	UCHAR	ScaTxs;					// MSCI Transmit Clock Src register value
	UCHAR	ScaIntCtrlRxDmaIntE;	// RX DMA Interrupt Control enable
	UCHAR	ScaIntCtrlRxDmia0E;		// RX DMIA bit pattern
	UCHAR	ScaIntCtrlRxDmib0E;		// RX DMIB bit pattern
	UCHAR	ScaIntCtrlTxDmaIntE;	// TX DMA Interrupt Control enable
	UCHAR	ScaIntCtrlTxDmia1E;		// TX DMIA bit pattern
	UCHAR	ScaIntCtrlTxDmib1E;		// TX DMIB bit pattern
	UCHAR	ScaIntCtrlRxIntE;		// RX MSCI Interrupt Control enable
	UCHAR	ScaIntCtrlTxIntE;		// TX MSCI Interrupt Control enable
	UCHAR	ScaIntCtrlTimerE;		// Timer Interrupt Control enable
	USHORT	IntMsciDmacMask;


	UCHAR	StationAddress1;		// Station address 1
	UCHAR	StationAddress2;		// Station address 2

	USHORT	TxIdleTimer;			// Timer for enable TX Idle interrupt
	USHORT	DropRtsTimer;			// Timer for dropping the RTS signal

	CHAR	IsRxTxEnable;
#define RXMSCI_ENABLE			0x01	//Bit 0 - Receiver disable/enable
#define RXDMA_ENABLE			0x02	//Bit 1 - Receive DMA disable/enable
#define RXDMA_INTE				0x04	//Bit 2 -
#define RXMSCI_INTE				0x08	//Bit 3 -
#define TXMSCI_ENABLE			0x10	//Bit 4 - Transmitter disable/enable
#define TXDMA_ENABLE			0x20	//Bit 5 - Transmit DMA disable/enable
#define TXDMA_INTE				0x40	//Bit 6 -
#define TXMSCI_INTE				0x80	//Bit 7 -

	USHORT			NumberOfDmaChains;		// Count of DMA descriptor chains
	LONG			RxCurDmaChains;

	PDMA_CHAIN		pRxRealDmaChainsArray;	// Ptr to first RX DMA Descriptor
	UCHAR			pRxDmaDspCpb;			// Receive Chain Pointer Base
	PDMA_CHAIN		pRxDmaDspCda;			// Current Descriptor Address
	PDMA_CHAIN		pRxDmaDspEda;			// Error Descriptor Address
	PSDLC_BUFFER	pRxRealSdlcBuffersArray;	// Ptr to first Receive buffer
	USHORT			RxDspIn;				// Receive descriptor IN index
	USHORT			RxDspOut;				// Receive descriptor OUT index

	USHORT			ReceivedFrames;			// Count of pending received frames
	USHORT			NumberOfTxFrames;		// Count of pending transmit frames

	PDMA_CHAIN		pTxRealDmaChainsArray;	// Ptr to first TX DMA Descriptor
	UCHAR			pTxDmaDspCpb;			// Receive Chain Pointer Base
	PDMA_CHAIN		pTxDmaDspCda;			// Current Descriptor address
	PDMA_CHAIN		pTxDmaDspEda;			// Error Descriptor address
	PSDLC_BUFFER	pTxRealSdlcBuffersArray;// Pointer to first TX buffer
	USHORT			TxDspIn;				// Transmit descriptor IN index
	USHORT			TxDspOut;				// Transmit descriptor OUT index

	UCHAR			TxWaitCts;				// Wait CTS up flag
											// TRUE - wait for CTS to come up
	UCHAR			TxWaitCtsDrop;			// Wait CTS down flag
											// TRUE - wait for CTS to come down
	UCHAR			DropRtsFlag;			// Flag for dropping the RTS signal
				// 0 - reset
				// 1 - Need to enable TX Idle INT
				// 2 - Need to enable one character time out interrupt
				// 3 - Need to drop RTS signal
											// FALSE- the CTS is up already
	DSMP_STATS			Stats;				// Statistics counters
	PCONTROLLER_EXT		pControllerExt;		// Ptr to this port's ControllerExt
	ULONG				Information;		// IRP information field to return

	ULONG				Adc;				// ADC (Analog to Digital Converter)
	ULONG				PortType;			// Interface Type

	USHORT				Isr01;
	UCHAR				Isr2;

	BOOLEAN				SignalService;		// Need to signal link service?
	BOOLEAN				CtsRequired;		// The Miniport Driver Does Not
	                                        // Need To Wait for CTS, if it
	                                        // Is coded with RTS_HIGH.  This
	                                        // is consistent with the SYNC
	                                        // port driver.

} DEVICE_EXT, *PDEVICE_EXT;

#else

typedef struct _CONTROLLER_EXTENSION
{

	UNICODE_STRING		Name;					//Board name
	WCHAR				NameBuffer[64];			//Board name (for debugging)
	LONG				AdapterLines;			//Number of ports on the card

	//
	// I/O Port information
	//
	PHYSICAL_ADDRESS	PhysIOPort;
	PUCHAR				VirtualIO;				//Mapped Base I/O address
	BOOLEAN				UnMapVirtualIO;			//Should we unmap the I/O ports
	UCHAR				IOSpan;

	//
	// Memory Window information
	//
	PHYSICAL_ADDRESS	PhysWindowAddress;
	PUCHAR				VirtualWindow;			//Mapped memory window
	BOOLEAN				UnMapVirtualWindow;		//Should we unmap the memory
	LONG				WindowSize;				//Mapped Window size
	KSPIN_LOCK			MemoryLock;				//Memory Window spinlock

	//
	// PLX chip information (PCI cards only)
	//
	PHYSICAL_ADDRESS	PhysPlxRegisters;
	PUCHAR				VirtualPlxRegisters;
	BOOLEAN				UnMapVirtualPlxRegisters;
	UCHAR				PlxRegistersSpan;

	//
	// SCA information
	//
	PHYSICAL_ADDRESS	ScaAddress;
	PUCHAR				VirtualSca;
	BOOLEAN				UnMapVirtualSca;

	//
	// Interrupt Line information
	//
	PHYSICAL_ADDRESS	PhysInterruptNumber;
	ULONG				InterruptVector;
	ULONG				InterruptVectorOriginal;
	PKINTERRUPT			InterruptObject;
	ULONG				InterruptLevelOriginal;
	KIRQL				InterruptLevel;
	KAFFINITY			ProcessorAffinity;
	KINTERRUPT_MODE		InterruptMode;
	BOOLEAN				InterruptShareable;		// Can we share the interrupt?

	//
	// PCI UIB information
	//
	ULONG				ConfigStream;
	ULONG				InterfaceID;

	//
	// An array of DeviceObject pointers
	//
	PDEVICE_OBJECT			pDeviceObject[4];
	struct _DEVICE_EXT *	pDeviceExt[4];

	//
	// Function pointers for IO for this controller.
	//
	UCHAR		(*pIO_IN) ();
	VOID		(*pIO_OUT) ();

	CHAR	NumberOfWindows;

	UCHAR	iBusMemoryCommType;		// card BUS, Memory, and communication type
	UCHAR	iSupportedHandshake;	// Supported handshake on the card
	UCHAR	oMemoryScaEnable;		// Memory and SCA chip enable
	UCHAR	oTxClkDtr01;			// TX Clock and DTR enable for port 0 and 1
	UCHAR	ioInterruptSelect;		// IRQ Level selected on the card
	UCHAR	ioMemorySelect;			// Memory window address selected on card
	UCHAR	oTxClkDtr23;			// TX Clock and DTR enable for port 2 and 3


	//
	// Misc Resource information
	//
	ULONG			BusNumber;
	ULONG			SlotNumber;
	INTERFACE_TYPE	BusType;
	HANDLE			hReportedResources;
	ULONG			DeviceID;
	BOOLEAN			InternalClocking[4];

	PUCHAR			pDigiDcdIntReg;		// DCD and Interrupt status register
	PUCHAR			pDigiMemScaReg;		// Memory and SCA chip enable register

	BOOLEAN			DPCRunning;			// Track if we are in the DPC

	UCHAR			SNALineSpeed[8];	// Temp line speed for SNA config
	UCHAR			DeviceName[8][DEV_NAME_LEN];	//  SNA Device Names

	PCONTROLLER_OBJECT	pControllerObj; // This Extensions contoller object

	LIST_ENTRY      ListElement;        // Queue the Controller to the global 
	                                    // controller list

} CONTROLLER_EXT, *PCONTROLLER_EXT;

//
// Port related information data structure
// This data structure is used to stored the information related to a
// particular port on the board. The Board level device object will used to
// handle the interrupt in the ISR, and the Port level device object will be
// used to access the port.
//
typedef struct _DEVICE_EXT
{
	WCHAR			NameBuffer[64];			// Line name
	UNICODE_STRING	Name;					// Line name
	UNICODE_STRING	SymbolicLinkName;		// Win32 app file handle name
	BOOLEAN			SymbolicLinkNameCreated;// TRUE, if the symbolic link
		                                    // name was created.
	WCHAR			SymLinkNameBuffer[64];
	LONG			DeviceOpens;			// Reference count for dev opens

	CHAR			PortNumber;			// Port number
#define FIRST_PORT              0
#define SECOND_PORT             1
#define THIRD_PORT              2
#define FOURTH_PORT             3

	CHAR			LineSpeed;			// Line speed
#define LS_2400BPS              2400
#define LS_4800BPS              4800
#define LS_9600BPS              9600
#define LS_19200BPS             19200
#define LS_38400BPS             38400
#define LS_56000BPS             56000
#define LS_64000BPS             64000
#define LS_128000BPS            128000
#define LS_256000BPS            256000
#define LS_512000BPS            512000
#define LS_1024000BPS           1024000
#define LS_1536000BPS           1536000
#define LS_2048000BPS           2048000

	BOOLEAN		InternalClocking;	// Internal Clocks if true
	UCHAR		LinkOptions;		// Link protocol parameters
	UCHAR		bSdlcCtrl;			// SDLC control field
	USHORT		FifoWatchdog;		// Drop RTS 
	PKEVENT		pUserEvent;			// Handle to Link Serive Driver
	IR			IR;					// Local Interface Record
	DSMP_CONFIG	Config;				// Config record (max frame, baud rate, etc)

	PSCA_REGS	pSca;				// Ptr to SCA registers
	PSCA_MSCI	pScaMsci;			// Ptr to the beginning of MSCI registers
	PSCA_TIMER	pScaTimer;			// Ptr to the beginning of Timer registers
	PSCA_DMAC	pScaRxDmac;			// Ptr to the beginning of Rx DMAC registers
	PSCA_DMAC	pScaTxDmac;			// Ptr to the beginning of Tx DMAC registers

	// DIGI card registers
	UCHAR	DigiMemScaE;			// Memory and SCA chip enable
	UCHAR	DigiDtrTxE;				// DTR and Transmit enable
	UCHAR	DigiTxClkInput;			// Transmit Clock input value
	UCHAR	DigiRegTxClkDtrCtrl;	// TX Clock and DTR control value
	UCHAR	DigiDcdMask;			// DCD signal mask
	UCHAR	DigiIntPendMask;		// SCA Interrupt Pending mask
	PUCHAR	DigiTxClkDtrCtrl;		// TX Clock and DTR Control register
	PUCHAR	DigiIntAckReg;			// SCA Interrupt Acknowledge register

	// Hitachi HD64570 Serial Communication Adapter (SCA)
	UCHAR	ScaMd0;					// MSCI Mode Register 0 value
	UCHAR	ScaMd1;					// MSCI Mode Register 1 value
	UCHAR	ScaMd2;					// MSCI Mode Register 2 value
	UCHAR	ScaCtl;					// MSCI Control Register value
	UCHAR	ScaTmc;					// MSCI Time constant register...
	UCHAR	ScaRxs;					// MSCI Receive Clock Source register value
	UCHAR	ScaTxs;					// MSCI Transmit Clock Src register value
	UCHAR	ScaIntCtrlRxDmaIntE;	// RX DMA Interrupt Control enable
	UCHAR	ScaIntCtrlRxDmia0E;		// RX DMIA bit pattern
	UCHAR	ScaIntCtrlRxDmib0E;		// RX DMIB bit pattern
	UCHAR	ScaIntCtrlTxDmaIntE;	// TX DMA Interrupt Control enable
	UCHAR	ScaIntCtrlTxDmia1E;		// TX DMIA bit pattern
	UCHAR	ScaIntCtrlTxDmib1E;		// TX DMIB bit pattern
	UCHAR	ScaIntCtrlRxIntE;		// RX MSCI Interrupt Control enable
	UCHAR	ScaIntCtrlTxIntE;		// TX MSCI Interrupt Control enable
	UCHAR	ScaIntCtrlTimerE;		// Timer Interrupt Control enable
	USHORT	IntMsciDmacMask;


	UCHAR	StationAddress1;		// Station address 1
	UCHAR	StationAddress2;		// Station address 2

	USHORT	TxIdleTimer;			// Timer for enable TX Idle interrupt
	USHORT	DropRtsTimer;			// Timer for dropping the RTS signal

	CHAR	IsRxTxEnable;
#define RXMSCI_ENABLE			0x01	//Bit 0 - Receiver disable/enable
#define RXDMA_ENABLE			0x02	//Bit 1 - Receive DMA disable/enable
#define RXDMA_INTE				0x04	//Bit 2 -
#define RXMSCI_INTE				0x08	//Bit 3 -
#define TXMSCI_ENABLE			0x10	//Bit 4 - Transmitter disable/enable
#define TXDMA_ENABLE			0x20	//Bit 5 - Transmit DMA disable/enable
#define TXDMA_INTE				0x40	//Bit 6 -
#define TXMSCI_INTE				0x80	//Bit 7 -

	USHORT			NumberOfDmaChains;		// Count of DMA descriptor chains
	LONG			RxCurDmaChains;

	PDMA_CHAIN		pRxRealDmaChainsArray;	// Ptr to first RX DMA Descriptor
	UCHAR			pRxDmaDspCpb;			// Receive Chain Pointer Base
	PDMA_CHAIN		pRxDmaDspCda;			// Current Descriptor Address
	PDMA_CHAIN		pRxDmaDspEda;			// Error Descriptor Address
	PSDLC_BUFFER	pRxRealSdlcBuffersArray;	// Ptr to first Receive buffer
	USHORT			RxDspIn;				// Receive descriptor IN index
	USHORT			RxDspOut;				// Receive descriptor OUT index

	USHORT			ReceivedFrames;			// Count of pending received frames
	USHORT			NumberOfTxFrames;		// Count of pending transmit frames

	PDMA_CHAIN		pTxRealDmaChainsArray;	// Ptr to first TX DMA Descriptor
	UCHAR			pTxDmaDspCpb;			// Receive Chain Pointer Base
	PDMA_CHAIN		pTxDmaDspCda;			// Current Descriptor address
	PDMA_CHAIN		pTxDmaDspEda;			// Error Descriptor address
	PSDLC_BUFFER	pTxRealSdlcBuffersArray;// Pointer to first TX buffer
	USHORT			TxDspIn;				// Transmit descriptor IN index
	USHORT			TxDspOut;				// Transmit descriptor OUT index

	UCHAR			TxWaitCts;				// Wait CTS up flag
											// TRUE - wait for CTS to come up
	UCHAR			TxWaitCtsDrop;			// Wait CTS down flag
											// TRUE - wait for CTS to come down
	UCHAR			DropRtsFlag;			// Flag for dropping the RTS signal
				// 0 - reset
				// 1 - Need to enable TX Idle INT
				// 2 - Need to enable one character time out interrupt
				// 3 - Need to drop RTS signal
											// FALSE- the CTS is up already
	DSMP_STATS			Stats;				// Statistics counters
	PCONTROLLER_OBJECT	pControllerObj;		// Ptr to this port's ControllerObj
	PCONTROLLER_EXT		pControllerExt;		// Ptr to this port's ControllerExt
	ULONG				Information;		// IRP information field to return

	ULONG				Adc;				// ADC (Analog to Digital Converter)
	ULONG				PortType;			// Interface Type

	USHORT				Isr01;
	UCHAR				Isr2;

	BOOLEAN				SignalService;		// Need to signal link service?
	BOOLEAN				CtsRequired;		// The Miniport Driver Does Not
	                                        // Need To Wait for CTS, if it
	                                        // Is coded with RTS_HIGH.  This
	                                        // is consistent with the SYNC
	                                        // port driver.

} DEVICE_EXT, *PDEVICE_EXT;


#endif // NT5_BUILD


// Prototypes

PVOID 
Dg570GetMappedAddress (
	IN INTERFACE_TYPE	BusType,
	IN ULONG			BusNumber,
	IN PHYSICAL_ADDRESS	IoAddress,
	IN ULONG			NumberOfBytes,
	IN ULONG			AddressSpace,
	OUT PBOOLEAN		MappedAddress);

#endif // BOARD_H_

