/*****************************************************************************
* Copyright (c) 1990-98 Digi International Inc., All Rights Reserved
* 
* This software contains proprietary and confidential information of Digi
* International Inc.  By accepting transfer of this copy, Recipient agrees
* to retain this software in confidence, to prevent disclosure to others,
* and to make no use of this software other than that for which it was
* delivered.  This is an unpublished copyrighted work of Digi International
* Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
* prohibited.
* 
* Restricted Rights Legend
*
* Use, duplication, or disclosure by the Government is subject to
* restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
* Technical Data and Computer Software clause at DFARS 252.227-7031 or
* subparagraphs (c)(1) and (2) of the Commercial Computer Software -
* Restricted Rights at 48 CFR 52.227-19, as applicable.
*
* Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
*
*****************************************************************************/

#include "stdafx.h"
#include "HWResources.h"

#ifdef _DEBUG
#undef THIS_FILE
static char THIS_FILE[]=__FILE__;
#define new DEBUG_NEW
#endif

BOOL SHWResources::Get(HKEY const hKey)
{
   BOOL fSuccess = FALSE;

   try
   {
      AffirmThrow(hKey != NULL);

      AffirmThrow(RegReadIntValue(hKey, DXB_REGVAL_BUS_TYPE, (int *)&eBusType, InterfaceTypeUndefined));
      AffirmThrow(RegReadDWordValue(hKey, DXB_REGVAL_BUS_NUMBER, &dwBusNumber));

      switch (eBusType)
      {
         case Isa:
         case Eisa:
         {
            REGVALUE aRegVals[] = 
            {
               { DXB_REGVAL_INTERRUPT,      &busSpecific.Isa.dwInterruptNumber,         sizeof(busSpecific.Isa.dwInterruptNumber),         REG_DWORD, 0 },
               { DXB_REGVAL_IO_ADDRESS,     &busSpecific.Isa.dwIOBaseAddress,           sizeof(busSpecific.Isa.dwIOBaseAddress),           REG_DWORD, 0 },
               { DXB_REGVAL_MEMORY_ADDRESS, &busSpecific.Isa.dwMemoryMappedBaseAddress, sizeof(busSpecific.Isa.dwMemoryMappedBaseAddress), REG_DWORD, 0 },
            };
            AffirmThrow(RegReadMultipleValues(hKey, aRegVals, ElementCount(aRegVals)));
            break;
         }

         case PCIBus:
         {
            REGVALUE aRegVals[] = 
            {
               { DXB_REGVAL_PCI_ID,       &busSpecific.Pci.dwPciID,        sizeof(busSpecific.Pci.dwPciID),       REG_DWORD,  0 },
               { DXB_REGVAL_SUBDEVICE_ID, &busSpecific.Pci.dwSubPciID,     sizeof(busSpecific.Pci.dwSubPciID),    REG_DWORD,  0 },
               { DXB_REGVAL_VENDOR_ID,    &busSpecific.Pci.dwVendorID,     sizeof(busSpecific.Pci.dwVendorID),    REG_DWORD,  0 },
               { DXB_REGVAL_SUBVENDOR_ID, &busSpecific.Pci.dwSubVendorID,  sizeof(busSpecific.Pci.dwSubVendorID), REG_DWORD,  0 },
               { DXB_REGVAL_BUS_NUMBER,   &busSpecific.Pci.dwBusNumber,    sizeof(busSpecific.Pci.dwBusNumber),   REG_DWORD,  0 },
               { DXB_REGVAL_SLOT_NUMBER,  &busSpecific.Pci.dwSlotNumber,   sizeof(busSpecific.Pci.dwSlotNumber),  REG_DWORD,  0 },
               { DXB_REGVAL_REVISION_ID,  &busSpecific.Pci.dwRevision,     sizeof(busSpecific.Pci.dwRevision),    REG_DWORD,  0 },
            };
            AffirmThrow(RegReadMultipleValues(hKey, aRegVals, ElementCount(aRegVals)));
            break;
         }

         default: AffirmThrow(FALSE); break;
      }

      fSuccess = TRUE;
   }
   catch (CAffirmException ae)
   {
   }

   return fSuccess;
}

BOOL SHWResources::Set(HKEY const hKey)
{
   BOOL fSuccess = FALSE;

   try
   {
      AffirmThrow(hKey != NULL);

      switch (eBusType)
      {
         case Isa:
         case Eisa:
         {
            REGVALUE aRegVals[] = 
            {
               { DXB_REGVAL_INTERRUPT,      (void *)busSpecific.Isa.dwInterruptNumber,         sizeof(busSpecific.Isa.dwInterruptNumber),         REG_DWORD,  0 },
               { DXB_REGVAL_IO_ADDRESS,     (void *)busSpecific.Isa.dwIOBaseAddress,           sizeof(busSpecific.Isa.dwIOBaseAddress),           REG_DWORD,  0 },
               { DXB_REGVAL_MEMORY_ADDRESS, (void *)busSpecific.Isa.dwMemoryMappedBaseAddress, sizeof(busSpecific.Isa.dwMemoryMappedBaseAddress), REG_DWORD,  0 },
            };
            AffirmThrow(RegWriteMultipleValues(hKey, aRegVals, ElementCount(aRegVals)));
            break;
         }

         case PCIBus:
         {
            REGVALUE aRegVals[] = 
            {
               { DXB_REGVAL_PCI_ID,       (void *)busSpecific.Pci.dwPciID,        sizeof(busSpecific.Pci.dwPciID),       REG_DWORD,  0 },
               { DXB_REGVAL_SUBDEVICE_ID, (void *)busSpecific.Pci.dwSubPciID,     sizeof(busSpecific.Pci.dwSubPciID),    REG_DWORD,  0 },
               { DXB_REGVAL_VENDOR_ID,    (void *)busSpecific.Pci.dwVendorID,     sizeof(busSpecific.Pci.dwVendorID),    REG_DWORD,  0 },
               { DXB_REGVAL_SUBVENDOR_ID, (void *)busSpecific.Pci.dwSubVendorID,  sizeof(busSpecific.Pci.dwSubVendorID), REG_DWORD,  0 },
               { DXB_REGVAL_BUS_NUMBER,   (void *)busSpecific.Pci.dwBusNumber,    sizeof(busSpecific.Pci.dwBusNumber),   REG_DWORD,  0 },
               { DXB_REGVAL_SLOT_NUMBER,  (void *)busSpecific.Pci.dwSlotNumber,   sizeof(busSpecific.Pci.dwSlotNumber),  REG_DWORD,  0 },
               { DXB_REGVAL_REVISION_ID,  (void *)busSpecific.Pci.dwRevision,     sizeof(busSpecific.Pci.dwRevision),    REG_DWORD,  0 },
            };
            AffirmThrow(RegWriteMultipleValues(hKey, aRegVals, ElementCount(aRegVals)));
            break;
         }

         default: AffirmThrow(FALSE); break;
      }

      fSuccess = TRUE;
   }
   catch (CAffirmException ae)
   {
   }

   return fSuccess;
}
