/*****************************************************************************
 * Copyright (c) 1988-95 Digi International Inc., All Rights Reserved
 * 
 * This  software  contains  proprietary  and  confidential   information   of
 * Digi International  Inc.   By  accepting  transfer  of this copy, Recipient
 * agrees to retain this software in  confidence,  to  prevent  disclosure  to
 * others,  and  to make no  use of this software other than that for which it
 * was delivered.  This is an unpublished copyright work  Digi   International
 * Inc.    Except   as   permitted   by  federal  law,  17 USC 117, copying is
 * strictly prohibited.
 * 
 * Digi  International  Inc.  CONFIDENTIAL  -   (Digi    International    Inc.
 * Confidential  when   combined   with   the   aggregated  modules  for  this
 * product) OBJECT CODE ONLY SOURCE MATERIALS
 * 
 * (C) COPYRIGHT Digi International Inc. 1995
 * 
 * All Rights Reserved
 * 
 * US   Government   Users   Restricted   Rights   -   Use,   duplication   or
 * disclosure  restricted by GSA ADP Schedule Contract with Digi International
 * Inc.
 * 
 *****************************************************************************/

/*
 *
 ******************************************************************
 *
 *   Embedded STREAMS Package
 *
 *   Copyright 1991  Spider Systems Limited
 *
 *   MASK.H
 *
 *   EPC Card
 *
 ******************************************************************

 *
 *
 *      %Q% %P%
 *      $Id: mask.h,v 1.3 1996/02/19 21:33:52 andyw Exp $
 *
 *      Last delta created       $Date: 1996/02/19 21:33:52 $
 *      This file extracted     %T% %H%
 *
 *      Modifications:
 *
 *      GCM     29 Oct 92       New file created
 *
 *
 *
 *

 *	Status register 
*/

#define		MASTERINTR	0x0001		/* Allows Interrupts */

#ifdef PRI
#define		SOFTINTR	0x0300		/* Software interrupt */
#define		TIMERINTR	0x0400		/* Timer Interrupt */
#define		HOSTINTR	0x0800		/* Host Interrupt */
#define		MUNICHINTR	0x1000		/* Munich-32s Interrupt */
#define		PACINTR		0x2000		/* PAC Chips Interrupt */
#define		PRISMINTR	0x4000		/* PRISM & HAWAII Interrupt */
#define		STACINTR	0x8000		/* STAC & UART Interrupt */
#define		CHIPINTR	(MUNICHINTR | PACINTR | PRISMINTR | STACINTR)
#else
#define		SOFTINTR	0x0300		/* Software interrupt */
#define		TIMERINTR	0x0400		/* Timer interrupt bit */
#define		SCAINTR		0x1800		/* SCA interrupt bit */
#define		HOSTINTR	0x2000		/* Host interrupt bit */
#define		CHIPINTR	(SCAINTR)
#endif

