#ifndef __DXBFR_
#define __DXBFR_


#ifndef TEXT
#define TEXT __T
#endif

enum {
	FRS_LINK_ENABLE_LINK = 0x0001,	 // always set
	FRS_LINK_ENABLE_STATS = 0x0002, // always set
	FRS_LINK_FLAGS_LMI_REV1 = 0x0004,	// Only 1 of these may be set
	FRS_LINK_FLAGS_GANG_OF_4 = 0x0008,	// Only 1 of these may be set
	FRS_LINK_FLAGS_ANNEX_D = 0x0010,	// Only 1 of these may be set
	FRS_LINK_FLAGS_MULTICAST = 0x0020, // not in use
	FRS_LINK_FLAGS_LMI_XON_XOFF = 0x0040,
	FRS_LINK_FLAGS_LMI_BANDWIDTH_CONTROL = 0x0080,
	FRS_LINK_FLAGS_DCE = 0x0100,
	FRS_LINK_FLAGS_BECN_XON_XOFF = 0x0200,
	FRS_LINK_FLAGS_FORCED_INJECTION = 0x0400,
	FRS_LINK_FLAGS_BUFFERED_INJECTION = 0x0800,
	FRS_LINK_FLAGS_STANDARD_INJECTION = 0x1000,
	FRS_LINK_FLAGS_IETF_ENCAPSULATION = 0x2000,	// always set
	FRS_LINK_FLAGS_ANNEX_A = 0x4000,	// Only 1 of these may be set
	LMIOnMask = 0x401C,
	LMIFLAGSMASK = 0x41DC,	// mask bits relavant to LMI page
	FRS_LINKS_FLAGS_ALWAYS_SET = 0x2003
};

//
// Frame Relay Line Configuration Parameters
//
#define DXB_REGKEY_FRAME_RELAY							TEXT( "FR" )

#define DXB_REGVAL_FR_LINK_FLAGS						TEXT( "flags" )
#define DXB_REGVAL_FR_LINK_FLAGS_TYPE					REG_DWORD
#define DXB_REGVAL_FR_LINK_FLAGS_DEFAULT				FRS_LINKS_FLAGS_ALWAYS_SET | FRS_LINK_FLAGS_BUFFERED_INJECTION

#define DXB_REGVAL_FR_LINK_LMI_DLCI						TEXT( "lmi_dlci" )
#define DXB_REGVAL_FR_LINK_LMI_DLCI_TYPE				REG_DWORD
#define DXB_REGVAL_FR_LINK_LMI_DLCI_DEFAULT				1023

#define DXB_REGVAL_FR_LINK_MAX_FRAMESIZE				TEXT( "max_frsize" )
#define DXB_REGVAL_FR_LINK_MAX_FRAMESIZE_TYPE			REG_DWORD
#define DXB_REGVAL_FR_LINK_MAX_FRAMESIZE_DEFAULT		2048

#define DXB_REGVAL_FR_LINK_MN1							TEXT( "mN1" )
#define DXB_REGVAL_FR_LINK_MN1_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MN1_DEFAULT					6

#define DXB_REGVAL_FR_LINK_MN2							TEXT( "mN2" )
#define DXB_REGVAL_FR_LINK_MN2_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MN2_DEFAULT					3

#define DXB_REGVAL_FR_LINK_MN3							TEXT( "mN3" )
#define DXB_REGVAL_FR_LINK_MN3_TYPE	  					REG_DWORD
#define DXB_REGVAL_FR_LINK_MN3_DEFAULT					4

#define DXB_REGVAL_FR_LINK_MN4							TEXT( "mN4" )
#define DXB_REGVAL_FR_LINK_MN4_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MN4_DEFAULT					1

#define DXB_REGVAL_FR_LINK_MP1							TEXT( "mP1" )
#define DXB_REGVAL_FR_LINK_MP1_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MP1_DEFAULT					64

#define DXB_REGVAL_FR_LINK_MP10							TEXT( "mP10" )
#define DXB_REGVAL_FR_LINK_MP10_TYPE					REG_DWORD
#define DXB_REGVAL_FR_LINK_MP10_DEFAULT					0

#define DXB_REGVAL_FR_LINK_MT1							TEXT( "mT1" )
#define DXB_REGVAL_FR_LINK_MT1_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MT1_DEFAULT					10

#define DXB_REGVAL_FR_LINK_MT2							TEXT( "mT2" )
#define DXB_REGVAL_FR_LINK_MT2_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MT2_DEFAULT					15

#define DXB_REGVAL_FR_LINK_MT3							TEXT( "mT3" )
#define DXB_REGVAL_FR_LINK_MT3_TYPE						REG_DWORD
#define DXB_REGVAL_FR_LINK_MT3_DEFAULT					10

#define DXB_REGVAL_FR_LINK_TSLOTMAP						TEXT( "tslotmap" )
#define DXB_REGVAL_FR_LINK_TSLOTMAP_TYPE				REG_DWORD
#define DXB_REGVAL_FR_LINK_TSLOTMAP_DEFAULT				0x00FFFFFF




#endif