/*****************************************************************************
* Copyright (c) 1990-2000 Digi International Inc., All Rights Reserved
* 
* This software contains proprietary and confidential information of Digi
* International Inc.  By accepting transfer of this copy, Recipient agrees
* to retain this software in confidence, to prevent disclosure to others,
* and to make no use of this software other than that for which it was
* delivered.  This is an unpublished copyrighted work of Digi International
* Inc.  Except as permitted by federal law, 17 USC 117, copying is strictly
* prohibited.
* 
* Restricted Rights Legend
*
* Use, duplication, or disclosure by the Government is subject to
* restrictions set forth in sub-paragraph (c)(1)(ii) of The Rights in
* Technical Data and Computer Software clause at DFARS 252.227-7031 or
* subparagraphs (c)(1) and (2) of the Commercial Computer Software -
* Restricted Rights at 48 CFR 52.227-19, as applicable.
*
* Digi International Inc. 11001 Bren Road East, Minnetonka, MN 55343
*
*****************************************************************************/

/*
 * $Id: dxbshare.h,v 1.9 1997/08/05 15:01:04 gary Exp $
 */

typedef uint32 memptr_t;
typedef uint32 memlen_t;

/*
 * xbus_init.bus_mode settings
 * 
 * BUS_USE_PLX_MAILBOXES can be OR'd in with any of the
 * BUS_SLAVE or BUS_MASTER_* settings to move dxb cmd and event 
 * queue pointers into PLX mailbox registers.  Note: this is a
 * feature of PCI cards only.  Do not use it on ISA cards.
 */
#define BUS_USE_PLX_MAILBOXES	0x80
#define BUS_MODE_MASK		(~BUS_USE_PLX_MAILBOXES)

#define BUS_MASTER_4KX32 	4
#define BUS_MASTER_128K  	3
#define	BUS_MASTER_4KX8	 	2
#define BUS_MASTER_32K	 	1
#define BUS_SLAVE	 	0 

#ifdef	PRI			
#define PLX_BASE		(0xA20E0000)
#else
#define	PLX_BASE		(0xA2020000)
#endif


#define PLX_DMA0_MODE_REG	(PLX_BASE + 0x100)	
#define PLX_DMA0_PCI_ADR_REG 	(PLX_BASE + 0x104)
#define PLX_DMA0_LOCAL_ADR_REG	(PLX_BASE + 0x108) 
#define PLX_DMA0_TRANS_SIZE_REG (PLX_BASE + 0x10C)	
#define PLX_DMA0_DESC_PTR_REG	(PLX_BASE + 0x110)	
#define PLX_DMA0_CMD_STAT_REG	(PLX_BASE + 0x128)	
#define	PLX_DMA_ARBITRATION_REG	(PLX_BASE + 0x12C)

/* These replace the previously defined value ROOTOFFSET. */
#define ROOTOFFSET_PRIME 	0x0300
#define ROOTOFFSET_CLYDE 	0x2E00


/*
// PLX Shared RunTime Registers
// Runtime registers are accessed at different offsets for host and local
// access.  Local access (e.g. from FEP) start at offset 0x80.  Host access
// starts at offset 0.
*/
#define PLX_REGS_BASE_LOCAL	(PLX_BASE+0x80)

#define PLX_MAILBOX_0 	0x40
#define PLX_MAILBOX_1	0x44
#define PLX_MAILBOX_2	0x48
#define PLX_MAILBOX_3	0x4C
#define PLX_MAILBOX_4	0x50
#define PLX_MAILBOX_5	0x54
#define PLX_MAILBOX_6	0x58
#define PLX_MAILBOX_7	0x5C


/*
// DXB Queue in/out pointers on DF PRIme are now located in the
// PLX Mailboxes 0-3.
*/

/* Host pointers */
#define DXB_MAILBOX_HOST_CMD_IN		(PLX_MAILBOX_0)
#define DXB_MAILBOX_HOST_CMD_OUT	(PLX_MAILBOX_1)
#define DXB_MAILBOX_HOST_EVENT_IN	(PLX_MAILBOX_2)
#define DXB_MAILBOX_HOST_EVENT_OUT	(PLX_MAILBOX_3)

/* FEP pointers */
#define DXB_MAILBOX_FEP_CMD_IN		(PLX_REGS_BASE_LOCAL+PLX_MAILBOX_0)
#define DXB_MAILBOX_FEP_CMD_OUT		(PLX_REGS_BASE_LOCAL+PLX_MAILBOX_1)
#define DXB_MAILBOX_FEP_EVENT_IN	(PLX_REGS_BASE_LOCAL+PLX_MAILBOX_2)
#define DXB_MAILBOX_FEP_EVENT_OUT	(PLX_REGS_BASE_LOCAL+PLX_MAILBOX_3)


/* Magic number */
#define IFMAGIC 0x12345678          /* Access check code */

/* Interface version */
#define IFVERSION        3          /* Interface version number */

/* Length of software name field */
#define IFNAMESZ        64          /* Name field length */


/* Root shared structure (length 128 bytes) */
/* Note: 32-bit addresses in the interface are all relative to the */
/*       start of this structure.                                  */


struct xbus_init {
	int8		board_ctl;
	int8		board_rsp;
	uint8		brd_intr;
	int8		bus_mode;	/* 0=Slave; 1=32k Master; 2=4kx8 Master */
	uint8		board_counter;  /* Board watchdog counter       */
	uint8		host_counter;   /* Host watchdog counter        */
	struct alloc	alloc_info;	/* Alloc_info goes here !	*/
        uint32		poll_host;      /* SW interrupt for board       */
};

struct shared
{
    /* Identification */
    uint8           if_ifversion;   /* 00: Interface version code */
    uint8           if_swversion;   /* 01: Software version */
    uint8           if_nbslot;      /* 02: Backplane slot number */
    uint8           if_nbident;     /* 03: Board type<<4 | sequence number */

    /* Access check */
    uint32          if_magic;       /* 04: "Magic number" */

    /* Host private info */
    uint32          if_hostbrd;     /* 08: Host's board handle */

    /* Diagnostic address block */
    uint32          if_diagaddr;    /* 0C: Address of diagnostic info */

    /* ASCII software name (padded with blanks) */
    uint8           if_swname[IFNAMESZ];
                                    /* 10: Software name */

    struct xbus_init xbus_init;     /* 50: Xbus structure */
};

/*
 * print_args is used by on board cmn_err and strlog to transfer
 * arguments across the bus.
 */
struct print_args {
	int16 mid, sid;
	int8 level;
	uint16 flags;
};

#define	CMD_PHYS_PAGES	32
typedef struct {
	uint32	start ;		/* Start of command buffer */
	uint32	max ;		/* Maximum chars in buffer */
	uint32	size ;		/* Size of buffer */
	uint32	in ;		/* Input pointer, host writes */
	uint32  out ;		/* Output pointer, board writes */
	int8	*phys_addrs[CMD_PHYS_PAGES] ; /* 4k Pages of Physical Mem */  
}DXB_CMD ;

#define EVENT_PHYS_PAGES 32 
typedef struct {
	uint32	start ;		/* Start of Event Buffer */
	uint32  max ;		/* Maximum chars in buffer */
	uint32  size ;		/* Size of Buffer */
	uint32	in ;		/* Input pointer, board writes */
	uint32  out ;		/* Output pointer, host writes */
	int8	*phys_addrs[EVENT_PHYS_PAGES] ; /* 4k pages of physical mem */
}DXB_EVENT ;


struct open_ctl {
	uint16	uid, gid;	/* From user area		*/
	uint16	ruid, rgid;	/* From user area		*/
	uint16	error;		/* To user area if != 0		*/
	
	uint16	pid, pgrp;	/* From proc structure		*/
	uint16	ttyval;		/* Returned *u.u_ttyp */
        int8	module[20];		/* module name for auto push */
};

/*
 * Commands
 */
#define	STE_OPEN	1
#define	STE_CLOSE	2
#define	STE_SEND	3
#define STE_MSG		4
#define STE_PUSH	5
#define STE_LINK	6
#define STE_REQ		7
#define STE_FLUSH	8
#define STE_FIND	9
#define STE_END_LINK	10
#define STE_PRINTF	11
#define STE_STRLOG	12
#define STE_CMNERR	13
#define STE_OPEN_ACK	20 
#define STE_CLOSE_ACK	21
#define	STE_POSITION_RPT 22
#define STE_NOTIFY      95L
#define STE_READY       96L
#define STE_RETURN      97L
#define STE_DUMMY	98
#define	STE_CLEANUP	99

/*
 * Errors - these are mapped on the host side into something appropriate
 */

#define	DEV_NOT_FOUND	1000

/*
 * Ioctl values - these probably belong in another file, but never mind
 */


#define		IS_PREFIX 	106 << 8    /* NOT a printable character! */
#define		IS_LINK		(IS_PREFIX | 1)
#define		IS_PUSH		(IS_PREFIX | 2)
#define		IS_GETID	(IS_PREFIX | 3)

/*
 * Misc constants
 */

#define ASYNCHRONOUS	0
#define SYNCHRONOUS	1

#if POWERPC
#define DXB_MSG_HEADER_LOC	(DXB_MSG_TYPE *)(0x00003FF0)
#define DXB_NOP_HEADER_LOC	(DXB_MSG_TYPE *)(0x00003FF8) 
#else

#if defined(EPC) && defined(ISA)
#define DXB_MSG_HEADER_LOC	(DXB_MSG_TYPE *)(0xA3000200)
#define DXB_NOP_HEADER_LOC	(DXB_MSG_TYPE *)(0xA3000208) 
#else
#define DXB_MSG_HEADER_LOC	(DXB_MSG_TYPE *)(0xA0000200)
#define DXB_NOP_HEADER_LOC	(DXB_MSG_TYPE *)(0xA0000208) 
#endif

#endif	/* POWERPC */
