### PortServer Diagnostics Test Descriptions

The following descriptions explain the test philosophy for each functional PortServer diagnostic test. The basic test is the same whether it is run from the video display or the front panel display.

#### Test 1 - Panel Light Test

This test cycles the 10 LEDs ON and OFF and both seven-segment displays in one second intervals. Since the LEDs and seven-segment displays are all write only, the operator must make a visual check of the indicators to ensure that they all cycle correctly. The pushbuttons are read by the test and checked for the non-depressed state (0).

#### Test 2 - Memory Test

Each pass of this test performs a pattern test and an address tag test to DRAM memory.

The byte pattern is incremented for each pass and is displayed on the front panel LEDs 0-7 (TD-RI). The pattern is written to 32K bytes beginning at address 08000h. The pattern is written again to 32K bytes beginning at address 30000h. The two 32K blocks are compared to determine pass or fail status.

The address tag test writes 32K bytes beginning at address 08000H. Address 08000h equals a 0h, 08001h equals a 1h, etc. This same tag pattern is written 32K times beginning at address 30000h. The two 32K blocks are compared to determine pass or fail status.

The word pattern is incremented for each pass and is displayed on the front panel LEDs 0-7 (TD-RI). The pattern is written to 32K words beginning at address 10000h. The pattern is written again to 32K words beginning at address 20000h. The two 64K blocks are compared to determine pass or fail status.

The address tag test writes 32K words beginning at address 10000h. Address 10000h equals a 0h, 10002h equals a 2h, etc. This same tag pattern is written 32K times beginning at address 20000h. The two 64K blocks are compared to determine pass or fail status.

#### Test 3 - Memory/DMA Test

This test uses DMA0 to move data from one memory location to another. The byte pattern is incremented for each pass and is displayed on the front panel LEDs 0-7 (TD-RI). The pattern is written to 32K bytes beginning at address 08000h. DMA0 is used to move 32K of data from 08000h to 10000h. When the move is complete, DMA0 interrupts and the two 32K blocks are compared to determine pass or fail status. If the DMA transfer is not completed within two seconds, a timeout error causes the test to fail.

#### Test 4 - Async Internal Test

This test is used to check out the 16550 async ports. The test puts the UART in loopback mode. The four output signals, DTR, RTS, OUT1, and OUT2 are looped back to the four input signal lines, CTS, DSR, RI and DCD. These signals are checked for high and low conditions. The UARTs are initialized to 9600 baud, 8 data bits, 1 stop bit, and no parity. Data is transmitted and received by the same UART.

Received data is compared to the transmitted data. As each port is being tested, port test results ("Pass/FAIL") are displayed. A failure on one or more ports is considered a test "FAIL."

#### Test 5 - Built-In UART External Loopback Test

Same as Test 4, but uses external loopback. From the front panel, press the right pushbutton to select the port to test. The display will cycle from "01" to "16" or highest UART plus "All". With the port selected, press the left pushbutton to start the test.

In Test 5 (Async External Test), each port loops back on itself instead of looping back between ports. This requires a test plug made from an RJ-45 connector at one end, with the pins wired as follows:

Output Pins | Connected To | Input Pins
Pin 3 (RTS) | connected to | Pin 1 (RI) and Pin 8 (CTS)
Pin 5 (SOUT) | connected to | Pin 6 (SIN)
Pin 9 (DTR) | connected to | Pin 10 (DCD)

#### Test 6 - NIC/DMA Test

This tests the 8390 NIC's ability to transmit, receive, and verify data in three diagnostic modes. To ensure that all test display information and test results are correct, the PortServer unit must be disconnected from the Ethernet network, and the PortServer’s Ethernet connector properly terminated.

#### Test 7 - Watchdog Timer Test

This test checks out the watchdog timer, a hardware feature used to ensure system reliability. The firmware must access PCS 5 within 1.6 seconds or the CPU will reset and jump to the reset vector (0FFFF0h).

It is up to the system to keep accessing PCS 5 to prevent it from resetting. This will force the POST diagnostic sequence to begin. This test allows the timer to expire. Normal test execution causes the user diagnostics to jump to the reset vector and begin the POST diagnostic sequence. The test will fail after three seconds if the timer has not expired.