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LD pd,(ps+HL)     Load     Rabbit 4000/5000 Instruction

Opcode	Instruction	Operation
--	LD pd,(ps+HL)	pd0=(ps+HL); pd1=(ps+HL+1) pd2=(ps+HL+2); pd3=(ps+HL+3)
6D 0A	LD PW,(PW+HL)	PW0=(ps+HL) PW1=(ps+HL+1) PW2=(ps+HL+2) PW3=(ps+HL+3)
6D 1A	LD PW,(PX+HL)
6D 2A	LD PW,(PY+HL)
6D 3A	LD PW,(PZ+HL)
6D 4A	LD PX,(PW+HL)	PX0=(ps+HL) PX1=(ps+HL+1) PX2=(ps+HL+2) PX3=(ps+HL+3)
6D 5A	LD PX,(PX+HL)
6D 6A	LD PX,(PY+HL)
6D 7A	LD PX,(PZ+HL)
6D 8A	LD PY,(PW+HL)	PY0=(ps+HL) PY1=(ps+HL+1) PY2=(ps+HL+2) PY3=(ps+HL+3)
6D 9A	LD PY,(PX+HL)
6D AA	LD PY,(PY+HL)
6D BA	LD PY,(PZ+HL)
6D CA	LD PZ,(PW+HL)	PZ0=(ps+HL) PZ1=(ps+HL+1) PZ2=(ps+HL+2) PZ3=(ps+HL+3)
6D DA	LD PZ,(PX+HL)
6D EA	LD PZ,(PY+HL)
6D FA	LD PZ,(PZ+HL)

Clocks	8-Bit Access	16-Bit Unaligned	16-Bit Aligned
Rabbit 4000	14	n/a	n/a
Rabbit 5000	15	15	13

Flags				ALTD			IOI/IOE
S	Z	L/V	C	F	R	SP	S	D
-	-	-	-		·

Description

Loads pd (any of the 32-bit registers PW, PX, PY or PZ) with the data whose address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

If ps is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).

The address is computed as the sum of ps and HL. HL is considered sign extended to 24 bits.