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LD (pd+d),rr     Load     Rabbit 4000/5000 Instruction

Opcode	Instruction	Operation
--	LD (pd+d),rr	(pd+d) = rrl; (pd+d+1) = rrh
6D 01 d	LD (PW+d),BC	(PW+d) = C; (PW+d+1) = B
6D 11 d	LD (PX+d),BC	(PX+d) = C; (PX+d+1) = B
6D 21 d	LD (PY+d),BC	(PY+d) = C; (PY+d+1) = B
6D 31 d	LD (PZ+d),BC	(PZ+d) = C; (PZ+d+1) = B
6D 41 d	LD (PW+d),DE	(PW+d) = E; (PW+d+1) = D
6D 51 d	LD (PX+d),DE	(PX+d) = E; (PX+d+1) = D
6D 61 d	LD (PY+d),DE	(PY+d) = E; (PY+d+1) = D
6D 71 d	LD (PZ+d),DE	(PZ+d) = E; (PZ+d+1) = D
6D 81 d	LD (PW+d),IX	(PW+d)=IXlow; (PW+d+1)=IXhigh
6D 91 d	LD (PX+d),IX	(PX+d)=IXlow; (PX+d+1)=IXhigh
6D A1 d	LD (PY+d),IX	(PY+d)=IXlow; (PY+d+1)=IXhigh
6D B1 d	LD (PZ+d),IX	(PZ+d)=IXlow; (PZ+d+1)=IXhigh
6D C1 d	LD (PW+d),IY	(PW+d)=IYlow; (PW+d+1)=IYhigh
6D D1 d	LD (PX+d),IY	(PX+d)=IYlow; (PX+d+1)=IYhigh
6D E1 d	LD (PY+d),IY	(PY+d)=IYlow; (PY+d+1)=IYhigh
6D F1 d	LD (PZ+d),IY	(PZ+d)=IYlow; (PZ+d+1)=IYhigH

Clocks	8-Bit Access	16-Bit Unaligned	16-Bit Aligned
Rabbit 4000	13	n/a	n/a
Rabbit 5000	14	13	12

Flags				ALTD			IOI/IOE
S	Z	L/V	C	F	R	SP	S	D
-	-	-	-

Description

Loads the memory location whose address is computed as the sum of pd and the 8-bit signed displacement d with rr (any of the 16-bit registers BC, DE, IX or IY).

The address is treated either as a logical address that will be passed through the MMU for translation into a physical address or as a physical address that does not need MMU translation.

If pd is 0xFFFFxxxx, i.e., the upper 16 bits are all ones, it represents a logical address. This is called a "long logical" address. Otherwise, it is a physical address with the low 20 bits or 24 bits being significant (depending on the memory available).