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SRL (IX+d)
SRL (IY+d)     Shift Right Logical     Rabbit 2000/3000/4000/5000 Instruction

Opcode	Instruction	Operation
DD CB d 3E	SRL (IX+d)	(IX + d) = {0,(IX + d)[7,1]} CF = (IX + d)[0]
FD CB d 3E	SRL (IY+d)	(IY + d) = {0,(IY + d)[7,1]} CF = (IY + d)[0]

Clocks	8-Bit Access	16-Bit Unaligned	16-Bit Aligned
Rabbit 2000/3000/4000	13	n/a	n/a
Rabbit 5000	14	12	10

Flags				ALTD			IOI/IOE
S	Z	L/V	C	F	R	SP	S	D
·	·	L	·	·			·	·

Description

Shifts to the right the bits of the data whose address is

• the sum of IX and the 8-bit signed displacement d, or

• the sum of IY and the 8-bit signed displacement d.

Each bit is shifted to the next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shifts to the C flag. Bit 7 is reset. See Figure 24 for an illustration.